View CY8C5248PVI-101_2327842.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary psoc ? 5: cy8c52 family data sheet programmable system-on-chip (psoc ? ) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-55034 rev. *a revised december 03, 2009 general description with its unique array of configurable blocks, psoc ? 5 is a true system level solution prov iding mcu, memory, analog, and digital peripheral functions in a single chip. the cy8c52 family offers a modern method of signal acquisi tion, signal processing, and c ontrol with high accuracy, high bandwidth, and high flexibility. analog capability spans the range from thermocouples (near dc voltage s) to ultrasonic signals. the cy8c52 family can handle dozens of data acquisition channels and analog inputs on every gpio pin. the cy8c52 family is also a high performance configurable digital syst em with some part numbers including interfaces such as usb, multi-master i 2 c, and can. in addition to communicat ion interfaces, the cy8c52 family has an easy to configure logic array, flexible routing to all i/o pins, and a high performance 32-bit arm ? cortex?-m3 microprocessor core . designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using psoc ? creator?, a hierarchical schematic design entry tool. the cy8c52 family provides unparalleled oppor tunities for analog and digital bill of materials integration w hile easily accommodating last minute design changes through simple firmware updates. features ? 32-bit arm cortex-m3 cpu core ? dc to 40 mhz operation ? flash program memory, up to 256 kb, 100,000 write cycles, 20 year retention, multiple security features ? up to 64 kb sram memory ? 2 kb eeprom memory, 1 million cycles, 20 ye ars retention ? 24 channel dma with multilayer ahb bus access ? programmable chained descriptors and priorities ? high bandwidth 32-bit transfer support ? low voltage, ultra low power ? wide operating voltage range: 0.5v to 5.5v ? high efficiency boost regulator from 0.5v input to 1.8v to 5.0v output ? 2 ma at 6 mhz ? low power modes including: ? 300 na hibernate mode with ram retention and lvd ? 2 a sleep mode with real time clock and low voltage reset ? versatile i/o system ? 28 to 72 i/o (62 gpio, 8 sio, 2 usbio [1] ) ? any gpio to any digital or analog peripheral routability ? lcd direct drive from any gpio, up to 46x16 segments [1] ? 1.2v to 5.5v i/o interface voltages, up to 4 domains ? maskable, independent irq on any pin or port ? schmitt trigger ttl inputs ? all gpio configurable as open drain high/low, pull up/down, high-z, or strong output ? configurable gpio pin state at power on reset (por) ? 25 ma sink on sio ? digital peripherals ? 20 to 24 programmable pld based universal digital blocks ? full can 2.0b 16 rx, 8 tx buffers [1] ? full-speed (fs) usb 2.0 12 mbps using internal oscillator [1] ? four 16-bit configurable timer, counter, and pwm blocks ? library of standard peripherals ? 8, 16, 24, and 32-bit timers, counters, and pwms ? spi, uart, i 2 c ? many others available in catalog ? library of advanced peripherals ? cyclic redundancy check (crc) ? pseudo random sequence (prs) generator ? lin bus 2.0 ? quadrature decoder ? analog peripherals (1.71v vdda 5.5v) ? 1.024v0.1% internal voltage reference across -40c to +85c (14 ppm/c) ? sar adc, 12-bit at 1 msps [1] ? two comparators with 75 ns response time ? programming, debug, and trace ? jtag (4 wire), serial wire de bug (swd) (2 wire), single wire viewer (swv), and traceport interfaces ? cortex-m3 flash patch and breakpoint (fpb) block ? cortex-m3 embedded trace macrocell? (etm?) gener- ates an instruction trace stream. ? cortex-m3 data watchpoint and trace (dwt) generates data trace information ? cortex-m3 instrumentation trace macrocell (itm) can be used for printf-style debugging ? dwt, etm, and itm blocks communicate with off-chip debug and trace systems via the swv or traceport ? bootloader programming supportable through i 2 c, spi, uart, usb, and other interfaces ? precision, programmable clocking ? 1 to 72 mhz internal 1% oscillator (over full temperature and voltage range) with pll ? 4 to 33 mhz crystal oscillator for crystal ppm accuracy ? internal pll clock generation up to 40 mhz ? 32.768 khz watch crystal oscillator ? low power internal oscillator at 1 khz, 100 khz ? temperature and packaging ? -40c to +85c degrees industrial temperature ? 48-pin ssop, 68-pin qfn, and 100-pin tqfp package options note 1. this feature on select devices only. see ordering information on page 79 for details. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 2 of 85 content overview 1. architectural overview ..... .............. .............. ........ 3 2. pinouts ............................................................................. 5 3. pin descriptions ........................................................... 9 4. cpu ................................................................................... 10 4.1 arm cortex-m3 cpu ............................................... 10 4.2 cache controller ...................................................... 12 4.3 dma and phub ....................................................... 12 4.4 interrupt controller ................................................... 14 5. memory .......................................................................... 15 5.1 static ram ............................................................... 15 5.2 flash program memory ............................................ 15 5.3 flash security ........................................................... 15 5.4 eeprom ...... ............... .............. .............. ........... ...... 16 5.5 external memory interface ....................................... 16 5.6 memory map ............................................................ 18 6. system integration ............. .............. .............. ......... 19 6.1 clocking system ....................................................... 19 6.2 power system .......................................................... 22 6.3 reset ........................................................................ 25 6.4 i/o system and routing ........................................... 26 7. digital subsystem ............. ........... ............ ........... ...... 32 7.1 example peripherals ................................................ 33 7.2 universal digital block ...... ........................................ 37 7.3 udb array description ............................................. 40 7.4 dsi routing interface descri ption ..... .............. ......... 41 7.5 can .......................................................................... 42 7.6 usb .......................................................................... 44 7.7 timers, counters, and pwms .................................. 45 7.8 i 2 c ............................................................................ 45 8. analog subsystem . .............. .............. .............. ......... 45 8.1 analog routing ......................................................... 46 8.2 successive approximation adc ............................... 48 8.3 comparators ............................................................. 48 8.4 lcd direct drive ...................................................... 49 8.5 capsense ................................................................. 50 8.6 temp sensor ............................................................ 50 9. programming, debug interfaces, resources ........................................................................ 51 9.1 jtag interface ......................................................... 51 9.2 swd interface .......................................................... 51 9.3 debug features ........................................................ 51 9.4 trace features ......................................................... 52 9.5 swv and traceport interfaces .......................... 52 9.6 programming features ............................................. 52 9.7 device security ............... ......................................... 52 10. development support ....... .............. .............. ........ 53 10.1 documentation ....................................................... 53 10.2 online ..................................................................... 53 10.3 tools ....................................................................... 53 11. electrical specifications ................................... 54 11.1 absolute maximum rating s .................................... 54 11.2 device level specifications .................................... 55 11.3 power regulators ............ ............... .............. .......... 57 11.4 inputs and outputs ................................................. 59 11.5 analog peripherals .......... ............... .............. .......... 63 11.6 digital peripherals .................................................. 66 11.7 memory .................................................................. 68 11.8 psoc system resources ....................................... 74 11.9 clocking ......................... ......................................... 76 12. ordering information ........................................... 79 12.1 part numbering conventions ........... .............. ........ 81 13. packaging ................................................................... 82 14. revision history ...................................................... 84 15. sales, solutions, and legal information .... 85 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 3 of 85 1. architectural overview introducing the cy8c52 family of ultra low power, flash programm able system-on-chip (psoc?) devices, part of a scalable 8-bit psoc ? 3 and 32-bit psoc 5 platform. the cy8c52 fa mily provides configurable blocks of ana log, digital, and interconnect circuitry around a cpu subsystem. the combi nation of a cpu with a very fl exible analog subsystem, digital subsystem, routing, and i/o enables a high level of integration in a wide vari ety of consumer, industrial, and medical applications. figure 1-1. simplified block diagram analog system lcd direct drive capsense temperature sensor - adc 4 x cmp + - system wide resources program debug & trace boundary scan program & debug 8051 or cortex m3 cpu interrupt controller phub dma cache controller sram flash eeprom emif cpu system memory system system bus digital interconnect analog interconnect 1.71 to 5.5v 0. 5 to 5.5v ( optional ) 4- 33 mhz (optional ) xtal osc 32.768 khz (optional ) rtc timer imo clock tree wdt and wake ilo clocking system 1.8v ldo smp por and lvd sleep power power management system usb phy d+ d- gpios gpios gpios gpios gpios gpios sio gpios sios sar adc can 2.0 i2c master/ slave universal digital block array (24 x udb) 4 x timer counter pwm fs usb 2.0 digital system udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb uart logic 12- bit pwm i2c slave 8- bit spi 12- bit spi logic 8- bit timer 16- bit prs udb 8- bit timer quadrature decoder 16- bit pwm sequencer usage example for udb udb udb udb udb udb udb udb udb [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 4 of 85 figure 1-1 illustrates the major components of the cy8c52 family. they are: ? arm cortex-m3 cpu subsystem ? nonvolatile subsystem ? programming, debug, and test subsystem ? inputs and outputs ? clocking ? power ? digital subsystem ? analog subsystem psoc?s digital subsystem provides half of its unique config- urability. it connects a digital signal from any peripheral to any pin through the digital system interconnect (dsi). it also provides functional flexibility through an array of small, fast, low power universal digital blocks (udbs). psoc creator provides a library of pre-built and tested standard digital peripherals (uart, spi, lin, prs, crc, timer, counter, pwm, and, or, and so on) that are mapped to the udb array. the designer can also easily create a digital circuit using boolean primitives by means of graphical design entry. each udb contains program- mable array logic (pal)/programmable logic device (pld) functionality, together with a small state machine engine to support a wide variety of peripherals. in addition to the flexibility of the udb array, psoc also provides configurable digital blocks targeted at specific functions. for the cy8c52 family these blocks can include four 16-bit timer, counter, and pwm blocks; i 2 c slave, master, and multi-master; full-speed usb; and full can 2.0b. for more details on the peripherals see the ?example periph- erals? section on page 33 of this data sheet. for information on udbs, dsi, and other digital blocks, see the ?digital subsystem? section on page 32 of this data sheet. psoc?s analog subsystem is the sec ond half of its unique config- urability. all analog performance is based on a highly accurate absolute voltage reference with less than 0.1% error over temperature and voltage. the configurable analog subsystem includes: ? analog muxes ? comparators ? analog mixers ? voltage references ? analog-to-digital converter (adc) all gpio pins can route analog signals into and out of the device using the internal analog bus. this allows the device to interface up to 62 discrete analog signals. the cy8c52 family offers a successive approximation register (sar) adc. featuring 12-bit conversions at up to 1m samples per second, it also offers low nonlinearity and offset errors and snr better than 70 db. it is well suited for a variety of higher speed analog applications. in addition to the adc, the an alog subsystem provides multiple comparators. see the ?analog subsystem? section on page 45 of this data sheet for more details. psoc?s cpu subsystem is built around a 32-bit three-stage pipelined arm cortex-m3 processor running at up to 40 mhz. the cortex-m3 includes a tightl y integrated nested vectored interrupt controller (nvic) and various debug and trace modules. the overall cpu subsystem includes a dma controller, flash cache, and ram. the nvic prov ides low latency, nested inter- rupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. the dma controller enables peripherals to exchange data without cpu involvement. this allows the cpu to run slower (saving power) or use those cpu cycles to improve the perfo rmance of firmware algorithms. the flash cache also reduces system power consumption by allowing less frequent flash access. psoc?s nonvolatile subsystem consists of flash, byte-writeable eeprom, and nonvolatile configurat ion options. it provides up to 256 kb of on-chip flash. the cpu can reprogram individual blocks of flash, enabling boot loaders. the designer can enable an error correcting code (ecc) for high reliability applications. a powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection . two kb of byte-writable eeprom is available on-chip to store application data. additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile me mory. this allows settings to activate immediately af ter power on reset (por). the three types of psoc i/o are extremely flexible. all i/os have many drive modes that are set at por. psoc also provides up to four i/o voltage domains through the vddio pins. every gpio has analog i/o, lcd drive, flexib le interrupt generation, slew rate control, and digital i/o capability. the sios on psoc allow voh to be set independently of vddio when used as outputs. when sios are in input mode they ar e high impedance. this is true even when the device is not powered or when the pin voltage goes above the supply voltage. this makes the sio ideally suited for use on an i 2 c bus where the psoc may not be powered when other devices on the bus are. the sio pins also have high current sink capability for applications such as led drives. the programmable input threshold feature of the sio can be used to make the sio function as a general purpose analog comparator. for devices with full-speed usb the usb physical interface is also provided (usbio). when not using usb these pins may also be used for limited digital functionality and device programming. all the features of the psoc i/os are covered in detail in the ?i/o system and routing? section on page 26 of this data sheet. the psoc device incorporates flexible internal clock generators, designed for high stability, and factory trimmed for absolute accuracy. the internal main oscillator (imo) is the master clock base for the system with 1% absolute accuracy at 3 mhz. the imo can be configured to run from 3 mhz up to 72 mhz. multiple clock derivatives can be gener ated from the main clock frequency to meet application needs. the device provides a pll to generate system clock frequencies up to 39 mhz (40 mhz including +1% tolerance) from the imo, external crystal, or external reference clock. it also contains a separate, very low power internal low speed oscillator (ilo) for the sleep and watchdog timers. a 32.768 khz external watch crystal is also supported for use in real time clock (rtc) applications. the [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 5 of 85 clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. the cy8c52 family supports a wide supply operating range from 1.71 to 5.5v. this allows operation from regulated supplies such as 1.8 5%, 2.5v 10%, 3.3v 10%, or 5.0v 10%, or directly from a wide range of battery type s. in addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5v. this enables the device to be powered directly from a single battery or solar cell. in addition, the de signer can use the boost converter to generate other voltages required by the device, such as a 3.3v supply for lcd glass drive. the bo ost?s output is available on the vboost pin, allowing other dev ices in the application to be powered from the psoc. psoc supports a wide range of low power modes. these include a 300 na hibernate mode with ram retention and a 2 a sleep mode with real time clock (rtc). in the second mode the optional 32.768 khz watch crystal runs continuously and maintains an accurate rtc. power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. this allows low power background processing when some peripherals are not in use. this, in turn, provides a total device current of only 2 ma when the cpu is running at 6mhz. the details of the psoc power modes are covered in the ?power system? section on page 22 of this data sheet. psoc uses jtag (4 wire) or se rial wire debug (swd) (2 wire) interfaces for programming, debug, and test. using these standard interfaces enables the designer to debug or program the psoc with a variety of hardware solutions from cypress or third party vendors. the cortex-m3 debug and trace modules include flash patch and breakpoint (fpb), data watchpoint and trace (dwt), embedded trace macrocell (etm), and instru- mentation trace macrocell (itm). these modules have many features to help solve difficult debug and trace problems. details of the programming, test, and debugging interfaces are discussed in the ?programming, debug interfaces, resources? section on page 51 of this data sheet. 2. pinouts the vddio pin that supplies a particular set of pins is indicated by the black lines drawn on the pinout diagrams in figure 2-1 through figure 2-3 . using the vddio pins, a single psoc can support multiple interface voltage levels, eliminating the need for off-chip level shifters. each vddio may sink up to 100 ma total to its associated i/o pins. on the 68 pin and 100 pin devices each set of vddio associated pins may sink up to 100 ma. the 48 pin device may sink up to 100 ma total for all vddio0 plus vddio2 associated i/o pins and 100 ma total for all vddio1 plus vddio3 associated i/o pins. figure 2-1. 48-pin ssop part pinout [2] ssop vssa (sio) p12[3] 247 vcca (gpio) p0[0] 346 p15[3] (gpio, khz xtal: xi) (gpio) p0[1] 445 p12[0] (sio, i2c1: scl) vddio0 742 p12[1] (sio, i2c1: sda) 643 (extref0, gpio) p0[3] p15[1] (gpio, mhz xtal: xi) (gpio) p0[5] 940 p15[0] (gpio, mhz xtal: xo) (gpio) p0[6] 10 39 vccd (gpio) p0[7] 11 38 vssd vccd 12 37 vddd vssd 13 36 p15[7] (usbio, d-, swdck) vddd 14 35 p15[6] (usbio, d+, swdio) (traceclk, gpio) p2[3] 15 34 p1[7] (gpio) (tracedata[0], gpio) p2[4] 16 33 p1[6] (gpio) vddio2 17 32 vddio1 (tracedata[1], gpio) p2[5] 18 31 p1[5] (gpio, ntrst) (tracedata[2], gpio) p2[6] 19 30 p1[4] (gpio, tdi) (tracedata[3], gpio) p2[7] 20 29 p1[3] (gpio, tdo, swv) vssb 21 28 ind 22 27 p1[1] (gpio, tck, swdck) vboost 23 26 p1[0] (gpio, tms, swdio) vbat 24 25 vdda (sio) p12[2] 148 vddio3 (gpio) p0[4] 841 p15[2] (gpio, khz xtal: xo) (gpio) p0[2] 544 lines show vddio to i/o supply association p1[2] (gpio, configurable xres) [2] [2] [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 6 of 85 figure 2-2. 68-pin qfn part pinout [3] (tracedata[2], gpio) p2[6] (tracedata[3], gpio) p2[7] (i2c0: scl, sio) p12[4] (i2c0: sda, sio) p12[5] vssb ind vboost vbat vssd xres (tms, swdio, gpio) p1[0] (tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] (tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] (ntrst, gpio) p1[5] vddio1 (gpio) p1[6] vccd (gpio) p3[3] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (gpio) p3[0] (gpio) p3[1] (extref1, gpio) p3[2] (gpio) p3[4] (gpio) p3[5] p0[3] (gpio, extref0) p0[2] (gpio) p0[1] (gpio) p0[0] (gpio) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) p12[1] (sio, i2c1: sda) p12[0] (sio, 12c1: scl) p3[7] (gpio) p3[6] (gpio) vddio3 p2[5] (gpio, tracedata[1]) vddio2 p2[4] (gpio, tracedata[0]) p2[3] (gpio, traceclk) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpoi) p15[4] (gpio) vddd vssd vccd p0[7] (gpio) p0[6] (gpio) p0[5] (gpio) p0[4] (gpio) vddio0 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view) lines show vddio to io supply association [2] [2] notes 2. pins are no connect (nc) on dev ices without usb. nc means that the pin has no electrical connection. the pin can be left floa ting or tied to a supply voltage or ground. 3. the center pad on the qfn package should be connected to digi tal ground (vssd) for best mechanica l, thermal, and electrical p erformance. if not connected to ground, it should be electrically float ed and not connected to any other signal. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 7 of 85 figure 2-3. 100-pin tqfp part pinout tqfp (tracedata[1], gpio) p2[5] (tracedata[2], gpio) p2[6] (tracedata[3], gpio) p2[7] (i2c0: scl, sio) p12[4] (i2c0: sda, sio) p12[5] (gpio) p6[4] (gpio) p6[5] (gpio) p6[6] (gpio) p6[7] vssb ind vboost vbat vssd xres (gpio) p5[0] (gpio) p5[1] (gpio) p5[2] (gpio) p5[3] (tms, swdio, gpio) p1[0] (tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] (tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] (ntrst, gpio) p1[5] vddio1 (gpio) p5[7] nc (extref1, gpio) p3[2] (gpio) p1[6] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (gpio) p5[4] (gpio) p5[5] (gpio) p5[6] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd vccd nc (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (gpio) p3[0] (gpio) p3[1] (gpio) p3[3] (gpio) p3[4] (gpio) p3[5] vddio3 vddio0 p0[3] (gpio, extref0) p0[2] (gpio) p0[1] (gpio) p0[0] (gpio) p4[1] (gpio) p4[0] (gpio) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca nc nc nc nc nc nc p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) p12[1] (sio, i2c1: sda) p12[0] (sio, i2c1: scl) p3[7] (gpio) p3[6] (gpio) vddio2 p2[4] (gpio, tracedata[0]) p2[3] (gpio, traceclk) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpio) p15[4] (gpio) p6[3] (gpio) p6[2] (gpio) p6[1] (gpio) p6[0] (gpio) vddd vssd vccd p4[7] (gpio) p4[6] (gpio) p4[5] (gpio) p4[4] (gpio) p4[3] (gpio) p4[2] (gpio) p0[7] (gpio) p0[6] (gpio) p0[5] (gpio) p0[4] (gpio) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 lines show vddio to io supply association [2] [2] [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 8 of 85 figure 2-4 and figure 2-5 show an example schematic and an example pcb layout, for the 100-pin tqfp part, for optimal analog performance on a 2-layer board. ? the two pins labeled vddd must be connected together. ? the two pins labeled vccd must be connected together, and have capacitors connected between them as shown in figure 2-4 and power system on page 22. the trace between the two vccd pins should be as short as possible. ? the two pins labeled vssd must be connected together. figure 2-4. example schematic for 100- pin tqfp part with power connections vssb 10 ind 11 vboost 12 vbat 13 vssd 14 xres 15 vddd 37 vssd 38 vccd 39 vcca 63 vssa 64 vdda 65 vssd 66 vccd 86 vssd 87 vddd 88 sio, p12[2] 67 sio, p12[3] 68 p4[0] 69 p4[1] 70 oa2out, p0[0] 71 oa0out, p0[1] 72 oa0+, p0[2] 73 oa0-, ref0, p0[3] 74 vddio0 75 oa2+, p0[4] 76 oa2-, p0[5] 77 idac0, p0[6] 78 idac2, p0[7] 79 p4[2] 80 p4[3] 81 p4[4] 82 p4[5] 83 p4[6] 84 p4[7] 85 p5[0] 16 p5[1] 17 p5[2] 18 p5[3] 19 p1[0], swio, tms 20 p1[1], swdio, tck 21 p1[2] 22 p1[3], swv, tdo 23 p1[4], tdi 24 p1[5], ntrst 25 vddio1 26 p1[6] 27 p1[7] 28 p12[6], sio 29 p12[7], sio 30 p5[4] 31 p5[5] 32 p5[6] 33 p5[7] 34 usb d+, p15[6] 35 usb d-, p15[7] 36 p6[7] 9 p6[0] 89 p6[1] 90 p6[2] 91 p6[3] 92 p15[4] 93 p15[5] 94 p2[0] 95 p2[1] 96 p2[2] 97 p2[3] 98 p2[4] 99 vddio2 100 p2[5] 1 p2[6] 2 p2[7] 3 p12[4], sio 4 p12[5], sio 5 p6[4] 6 p6[5] 7 p6[6] 8 nc 40 nc 41 p15[0], mhzxout 42 p15[1], mhzxin 43 p3[0], idac1 44 p3[1], idac3 45 p3[2], oa3-, ref1 46 p3[3], oa3+ 47 p3[4], oa1- 48 p3[5], oa1+ 49 vddio3 50 oa1out, p3[6] 51 oa3out, p3[7] 52 sio, p12[0] 53 sio, p12[1] 54 khzxout, p15[2] 55 khzxin, p15[3] 56 nc 57 nc 58 nc 59 nc 60 nc 61 nc 62 u2 cy8c55xx vssd vdda vcca vccd vssd vddd vssd vddd vddd vssd vssa vssa vssd vssd vssd vssd 0.1uf c8 vssd vddd vddd vddd vddd vddd vssd 1uf c9 0.1uf c10 0.1uf c11 0.1uf c16 0.1uf c12 0.1uf c6 0.1uf c2 1uf c15 1uf c1 vssd vddd vssd vddd vdda vssd vccd vssd 0.1uf c3 vssa vdda 1uf c13 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 9 of 85 figure 2-5. example pcb layout for 100-pin tqfp part for optimal analog performance 3. pin descriptions extref0, extref1. external reference input to the analog system. gpio. general purpose i/o pin provi des interfaces to the cpu, digital peripherals, analog peripherals, interrupts, lcd segment drive, and capsense ?[4] . i2c0: scl, i2c1: scl. i 2 c scl line providing wake from sleep on an address match. any i/o pin can be used for i 2 c scl if wake from sleep is not required. i2c0: sda, i2c1: sda. i 2 c sda line providing wake from sleep on an address match. any i/o pin can be used for i 2 c sda if wake from sleep is not required. ind. inductor connection to boost pump. khz xtal: xo, khz xtal: xi. 32.768 khz crystal oscillator pin. mhz xtal: xo, mhz xtal: xi. 4 to 33 mhz crystal oscillator pin. ntrst. optional jtag test reset programming and debug port connection to reset the jtag connection. sio. special i/o provides interfaces to the cpu, digital periph- erals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. swdck. serial wire debug clock programming and debug port connection. swdio. serial wire debug input and output programming and debug port connection. tck. jtag test clock programming and debug port connection. tdi. jtag test data in programming and debug port connection. tdo. jtag test data out programming and debug port connection. tms. jtag test mode select programming and debug port connection. traceclk. cortex-m3 traceport connection, clocks tracedata pins. tracedata[3:0]. cortex-m3 traceport connections, output data. swv. single wire viewer output. usbio, d+. provides d+ connection directly to a usb 2.0 bus. may be used as a digital i/o pin; it is powered from vddd instead of from a vddio. pins are no connect (nc) on devices without usb. [2] usbio, d-. provides d- connection directly to a usb 2.0 bus. may be used as a digital i/o pin; it is powered from vddd instead of from a vddio. pins are no connect (nc) on devices without usb. [2] vboost. power sense connection to boost pump. vbat. battery supply to boost pump. vcca. output of analog core regulator and input to analog core. requires a 1 f capacitor to vssa. regulator output not for external use. vccd. output of digital core regulator and input to digital core. requires a capacitor from each vccd pin to vssd; see power system on page 22. regulator output not for external use. vdda. supply for all analog peripherals and analog core regulator. vdda must be the highest voltage present on the device. all other supply pins must be less than or equal to vdda. vddd vssd vdda vssa vssd plane vssa plane note 4. gpios with opamp outputs are not recommended for use with capsense. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 10 of 85 vddd. supply for all digital peripherals and digital core regulator. vddd must be less than or equal to vdda. vssa. ground for all analog peripherals. vssb. ground connection for boost pump. vssd. ground for all digital logic and i/o pins. vddio0, vddio1, vddio2, vddio3. supply for i/o pins. see pinouts for specific i/o pin to vddio mapping. vddio must be less than or equal to vdda. xres (and configurable xres ). external reset pin. active low with internal pullup. in 48-pin ssop parts, p1[2] is configured as xres . in all other parts the pin is configured as a gpio. 4. cpu 4.1 arm cortex-m3 cpu the cy8c52 family of devices has an arm cortex-m3 cpu core. the cortex-m3 is a low power 32-bit three-stage pipelined harvard architecture cpu that delivers 1.25 dmips/mhz. it is intended for deeply embedded applications that require fast interrupt handling features. figure 4-1. arm cortex-m3 block diagram the cortex-m3 cpu subsystem includes these features: ? arm cortex-m3 cpu ? programmable nested vectored interrupt controller (nvic), tightly integrated with the cpu core ? full featured debug and trace modules, tightly integrated with the cpu core ? up to 256 kb of flash memory, 2 kb of eeprom, and 64 kb of sram ? cache controller ? peripheral hub (phub) ? dma controller ? external memory interface (emif) nested vectored interrupt controller (nvic) debug block (serial and jtag) embedded trace module (etm) trace port interface unit (tpiu) interrupt inputs jtag/swd trace pins: 5 for traceport or 1 for swv mode cortex m3 cpu core i- bus s- bus d- bus 256 kb ecc flash cache 32 kb sram dma ahb bridge & bus matrix phub gpio & emif prog. digital prog. analog special functions peripherals ahb spokes ahb ahb ahb bus matrix cortex m3 wrapper c- bus data watchpoint and trace (dwt) instrumentation trace module (itm) flash patch and breakpoint (fpb) bus matrix 32 kb sram bus matrix [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 11 of 85 4.1.1 cortex-m3 features the cortex-m3 cpu features include: ? 4 gb address space. predefined address regions for code, data, and peripherals. multiple buses for efficient and simulta- neous accesses of instructions, data, and peripherals. ? the thumb ? -2 instruction set, which offers arm-level perfor- mance at thumb-level code density. this includes 16-bit and 32-bit instructions. advanced instructions include: ? bit-field control ? hardware multiply and divide ? saturation ? if-then ? wait for events and interrupts ? exclusive access and barrier ? special register access the cortex-m3 does not support arm instructions. ? bit-band support. atomic bit- level write and read operations. ? unaligned data storage and access. contiguous storage of data of different byte lengths. ? operation at two privilege levels (privileged and user) and in two modes (thread and handler). some instructions can only be executed at the privileged le vel. there are also two stack pointers: main (msp) and pr ocess (psp). these features support a multitasking operating system running one or more user-level processes. ? extensive interrupt and system exception support. 4.1.2 cortex-m3 operating modes the cortex-m3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in table 4-1 . at the user level, access to cert ain instructions, special registers, configuration registers, and debugging components is blocked. attempts to access them cause a fault exception. at the privi- leged level, access to all instructions and registers is allowed. the processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not. 4.1.3 cpu registers the cortex-m3 cpu registers are listed in table 4-2 . registers r0-r15 are all 32 bits wide. table 4-1. operational level condition privileged user running an exception handler mode not used running main program thread mode thread mode table 4-2. cortex m3 cpu registers register description r0-r12 general purpose registers r0-r12 have no special architecturally defined uses. most instructions that specify a general purpose register specify r0-r12. ? low registers: registers r0-r7 are acces- sible by all instructions that specify a general purpose register. ? high registers: registers r8-r12 are acces- sible by all 32-bit instr uctions that specify a general purpose register; they are not acces- sible by all 16-bit instructions. r13 r13 is the stack pointer register. it is a banked register that switches between two 32-bit stack pointers: the main stack pointer (msp) and the process stack pointer (psp). the psp is used only when the cpu operates at the user level in thread mode. the msp is used in all other privilege levels and modes. bits[0:1] of the sp are ignored and considered to be 0, so the sp is always aligned to a word (4 byte) boundary. r14 r14 is the link register (lr). the lr stores the return address when a subroutine is called. r15 r15 is the program counter (pc). bit 0 of the pc is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. xpsr the program status registers are divided into three status registers, which are accessed either together or separately: ? application program status register (apsr) holds program execution status bits such as zero, carry, negative, in bits[27:31]. ? interrupt program status register (ipsr) holds the current exception number in bits[0:8]. ? execution program status register (epsr) holds control bits for interrupt continuable and if-then instructions in bits[10:15] and [25:26]. bit 24 is always set to 1 to indicate thumb mode. trying to clear it causes a fault exception. primask a 1-bit interrupt mask register. when set, it allows only the nonmaskable interrupt (nmi) and hard fault exception. all other exceptions and interrupts are masked. faultmask a 1-bit interrupt mask register. when set, it allows only the nmi. all other exceptions and interrupts are masked. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 12 of 85 4.2 cache controller the cy8c52 family adds an inst ruction cache between the cpu and the flash memory. this gua rantees a faster instruction execution rate. the flash ca che also reduces system power consumption by requiring less frequent flash access. 4.3 dma and phub the phub and the dma controller are responsible for data transfer between the cpu and peripherals, and also data transfers between peripherals. the phub and dma also control device configuration during boot. the phub consists of: ? a central hub that includes the dma controller, arbiter, and router ? multiple spokes that radiate outward from the hub to most peripherals there are two phub masters: the cpu and the dma controller. both masters may initiate tr ansactions on the bus. the dma channels can handle peripheral communication without cpu intervention. the arbiter in t he central hub determines which dma channel is the highest priority if there are multiple requests. 4.3.1 phub features ? cpu and dma controller are both bus masters to the phub ? eight multi-layer ahb bus para llel access paths (spokes) for peripheral access ? simultaneous cpu and dma access to peripherals located on different spokes ? simultaneous dma source and destination burst transactions on different spokes ? supports 8, 16, 24, and 32-bit addressing and data 4.3.2 dma features ? 24 dma channels ? each channel has one or more transaction descriptors (tds) to configure channel behavior. up to 128 total tds can be defined ? tds can be dynamically updated ? eight levels of priority per channel ? any digitally routable signal, the cpu, or another dma channel, can trigger a transaction ? each channel can generate up to two interrupts per transfer ? transactions can be stalled or canceled ? supports transaction size of infinite or 1 to 64k bytes ? large transactions may be broken into smaller bursts of 1 to 127 bytes ? tds may be nested and/or chained for complex transactions 4.3.3 priority levels the cpu always has higher pr iority than the dma controller when their accesses require the same bus resources. due to the system architecture, the cpu can never starve the dma. dma channels of higher priority (lower priority number) may interrupt current dma transfers. in the case of an interrupt, the current transfer is allowed to complete its current transaction. to ensure latency limits when multiple dma accesses are requested simul- taneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. if a tie occurs on two dma requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. the round robin allocation can be disabled for each dma channel, allowing it to always be at the head of the line. priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in table 4-4 after the cpu and dma priority levels 0 and 1 have satisfied their requirements. when the fairness algorithm is disabled, dma access is granted based solely on the priority level; no bus bandwidth guarantees are made. basepri a register of up to nine bits that define the masking priority level. when set, it disables all interrupts of the same or higher priority value. if set to 0 then the masking function is disabled. control a 2-bit register for controlling the operating mode. bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. bit 1: 0 = default stack (msp) is used, 1 = alternate stack is used. if in thread mode or user level then the alternate stack is the psp. there is no alternate stack for handler mode; the bit must be 0 while in handler mode. table 4-2. cortex m3 cpu registers (continued) register description table 4-3. phub spokes and peripherals phub spokes peripherals 0 sram 1 ios , picu , emif 2 phub local configuration, power manager , clocks , ic , swv , eeprom , flash programming interface 3 analog interface and trim , decimator 4 usb , can , i 2 c , timers, counters, and pwms 5 reserved 6 udbs group 1 7 udbs group 2 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 13 of 85 4.3.4 transaction modes supported the flexible configuration of each dma channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. general us e cases include, but are not limited to: 4.3.4.1 simple dma in a simple dma case, a single td transfers data between a source and sink (peripherals or memory location). 4.3.4.2 auto repeat dma auto repeat dma is typically used when a static pattern is repet- itively read from system memory and written to a peripheral. this is done with a single td that chains to itself. 4.3.4.3 ping pong dma a ping pong dma case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. in its simplest form, this is done by chaining two tds together so that each td calls the opposite td when complete. 4.3.4.4 circular dma circular dma is similar to ping pong dma except it contains more than two buffers. in this case th ere are multiple tds; after the last td is complete it chai ns back to the first td. 4.3.4.5 indexed dma in an indexed dma case, an external master requires access to locations on the system bus as if those locations were shared memory. as an example, a peripheral may be configured as an spi or i 2 c slave where an address is received by the external master. that address becomes an i ndex or offset into the internal system bus memory space. this is accomplished with an initial ?address fetch? td that reads the target address location from the peripheral and writes that va lue into a subsequent td in the chain. this modifies the td chain on the fly. when the ?address fetch? td completes it moves on to the next td, which has the new address information embedded in it. this td then carries out the data transfer with the address location required by the external master. 4.3.4.6 scatter gather dma in the case of scatter gather dma, there are multiple noncon- tiguous sources or destinations that are required to effectively carry out an overall dma transaction. for example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. scatter gather dma allows the segments to be concatenated together by using multiple tds in a chain. the chain gathers the data from the multiple locations. a similar concept applies for the reception of data onto the device. certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. each td in the chain specifies the location for each discrete element in the chain. 4.3.4.7 packet queuing dma packet queuing dma is similar to scatter gather dma but specif- ically refers to packet protocols. with these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. for instance, to transmit a packet, a memory mapped configu- ration register can be written insi de a peripheral, specifying the overall length of the ensuing data phase. the cpu can set up this configuration information anywhere in system memory and copy it with a simple td to the peripheral. after the configuration phase, a data phase td (or a series of data phase tds) can begin (potentially using scatter gather). when the data phase td(s) finish, a status phase td can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in syst em memory specified by the cpu for later inspection. multiple se ts of configuration, data, and status phase ?subchains? can be strung together to create larger chains that transmit multiple packets in this way. a similar concept exists in the opposite di rection to receive the packets. 4.3.4.8 nested dma one td may modify another td, as the td configuration space is memory mapped similar to any other peripheral. for example, a first td loads a second td?s configuration and then calls the second td. the second td moves data as required by the appli- cation. when complete, the second td calls the first td, which again updates the second td?s configuration. this process repeats as often as necessary. table 4-4. priority levels priority level % bus bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4 12.5 56.2 63.1 71.5 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 14 of 85 4.4 interrupt controller the cortex-m3 nvic supports 16 system exceptions and 32 interrupts from peripherals, as shown in ta b l e 4 - 5 . bit 0 of each exception vector i ndicates whether the exception is executed using arm or thum b instructions. because the cortex-m3 only supports thumb instructions, this bit must always be 1. the cortex-m3 non maskable interrupt (nmi) input can be routed to any pin, via the dsi, or disconnected from all pins. see ?dsi routing inte rface description? section on page 41. the nested vectored interrupt controller (nvic) handles inter- rupts from the peripherals, and passes the interrupt vectors to the cpu. it is closely integrated with the cpu for low latency interrupt handling. features include: ? 32 interrupts. multiple so urces for each interrupt. ? configurable number of priority levels: from 3 to 8. ? dynamic reprioritization of interrupts. ? priority grouping. this allows selection of preempting and non preempting interrupt levels. ? support for tail-chaining, and late arrival, of interrupts. this enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. if the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. each interrupt vector may choose from three interrupt sources: fixed function, dma, and udb. the fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. the dma interrupt sources provide direct connections to the two dma interrupt sources provided per dma channel. the thir d interrupt source for vectors is from the udb digital routing array. this allows any digital signal available to the udb array to be used as an interrupt source. all interrupt sources may be routed to any interrupt vector using the udb interrupt source connections. table 4-5. cortex-m3 exceptions and interrupts exception number exception type priority exception table address offset function 0x00 starting value of r13 / msp 1 reset -3 (highest) 0x04 reset 2 nmi -2 0x08 non maskable interrupt 3 hard fault -1 0x0c all classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked 4 memmanage programmable 0x10 memory managem ent fault, for example, instruction fetch from a nonexecutable region 5 bus fault programmable 0x14 error response received from the bus system; caused by an instruction prefetch abort or data access error 6 usage fault programmable 0x18 typically caused by invalid instructions or trying to switch to arm mode 7 ? 10 - - 0x1c ? 0x28 reserved 11 svc programmable 0x2c system serv ice call via svc instruction 12 debug monitor programmable 0x30 debug monitor 13 - - 0x34 reserved 14 pendsv programmable 0x38 deferred request for system service 15 systick programmable 0x3c system tick timer 16 ? 47 irq programmable 0x40 ? 0x3fc peripheral interrupt request #0 - #31 table 4-6. interrupt vector table interrupt # cortex-m3 exception # fixed function dma udb 0 16 low voltage detect (lvd) phub_termout0[0] udb_intr[0] 1 17 cache/ecc phub_termout0[1] udb_intr[1] 218 reserved phub_termout0[2] udb_intr[2] 3 19 sleep (pwr mgr) phub_termout0[3] udb_intr[3] 4 20 picu[0] phub_termout0[4] udb_intr[4] 5 21 picu[1] phub_termout0[5] udb_intr[5] 6 22 picu[2] phub_termout0[6] udb_intr[6] [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 15 of 85 5. memory 5.1 static ram cy8c52 static ram (sram) is us ed for temporary data storage. code can be executed at full speed from the portion of sram that is located in the code spac e. this process is slower from sram above 0x20000000. the device provides up to 64 kb of sram. the cpu or the dma controller can access all of sram. the sram can be accessed simultaneously by the cortex-m3 cpu and the dma controller if accessing different 32 kb blocks. 5.2 flash program memory flash memory in psoc devices pr ovides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ecc data. the main flash memory area contains up to 256 kb of user program space. up to an additional 32 kb of flash space is available for error correcting codes (ecc). if ecc is not used this space can store device configuration data and bulk user data. user code may not be run out of the ecc flash memory section. ecc can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. the flash output is 9 bytes wide with 8 bytes of data and 1 byte of ecc data. the cpu or dma controller read both user code and bulk data located in flash through the ca che controller. this provides higher cpu performance. if ecc is enabled, the cache controller also performs error checking and correction. flash programming is performed through a special interface and preempts code execution out of flash. code execution out of cache may continue during flash programm ing as long as that code is contained inside the cache. the flash programming interface performs flash erasing, programming and setting code protection levels. flash in system serial programming (issp), typically used for production programming, is possible through both the swd and jtag inter- faces. in-system programming, typically used for bootloaders, is also possible using serial interfaces such as i 2 c, usb, uart, and spi, or any communications protocol. 5.3 flash security all psoc devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. this prevents duplication or reverse engineering of proprietary code. flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ecc or configu- ration data. the device offers the ability to assign one of four protection levels to each row of flash. table 5-1 lists the protection modes available. flash protection lev els can only be changed by performing a complete flash erase. the full protection and field upgrade settings disable external access (through a debugging 7 23 picu[3] phub_termout0[7] udb_intr[7] 8 24 picu[4] phub_termout0[8] udb_intr[8] 9 25 picu[5] phub_termout0[9] udb_intr[9] 10 26 picu[6] phub_termout0[10] udb_intr[10] 11 27 picu[12] phub_termout0[11] udb_intr[11] 12 28 picu[15] phub_termout0[12] udb_intr[12] 13 29 comparator int phub_termout0[13] udb_intr[13] 14 30 reserved phub_termout0[14] udb_intr[14] 15 31 i 2 c phub_termout0[15] udb_intr[15] 16 32 can phub_termout1[0] udb_intr[16] 17 33 timer/counter0 phub_termout1[1] udb_intr[17] 18 34 timer/counter1 phub_termout1[2] udb_intr[18] 19 35 timer/counter2 phub_termout1[3] udb_intr[19] 20 36 timer/counter3 phub_termout1[4] udb_intr[20] 21 37 usb sof int phub_termout1[5] udb_intr[21] 22 38 usb arb int phub_termout1[6] udb_intr[22] 23 39 usb bus int phub_termout1[7] udb_intr[23] 24 40 usb endpoint[0] phub_termout1[8] udb_intr[24] 25 41 usb endpoint data phub_termout1[9] udb_intr[25] 26 42 reserved phub_termout1[10] udb_intr[26] 27 43 reserved phub_termout1[11] udb_intr[27] 28 44 reserved phub_termout1[12] udb_intr[28] 29 45 decimator int phub_termout1[13] udb_intr[29] 30 46 phub_err_int phub_termout1[14] udb_intr[30] 31 47 eeprom_fault_int phub_termout1[15] udb_intr[31] table 4-6. interrupt vector table (continued) interrupt # cortex-m3 exception # fixed function dma udb [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 16 of 85 tool such as psoc creator, fo r example). if your application requires code update through a boot loader, then use the field upgrade setting. use the unprotected setting only when no security is needed in your application. the psoc device also offers an advanced security feat ure called device security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the ?device security? section on page 52). for more information on how to take full advantage of th e security features in psoc, see the psoc 5 trm. disclaimer note the following details of t he flash code protection features on cypress devices. cypress products meet the spec ifications contained in their particular cypress data sheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaran- teeing the product as ?unbreakable.? cypress is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress are committed to continuously improving the code protecti on features of our products. 5.4 eeprom psoc eeprom memory is a byte addressable nonvolatile memory. the cy8c52 has 2 kb of eeprom memory to store user data. reads from eeprom are random access at the byte level. reads are done directly; writes are done by sending write commands to an eeprom programming interface. cpu code execution can continue from flash during eeprom writes. eeprom is erasable and writeable at the row level. the eeprom is divided into two sections, each containing 64 rows of 16 bytes each. the cpu can not execute out of eeprom. there is no ecc hardware associated with eeprom. if ecc is required it must be handled in firmware. 5.5 external memory interface cy8c52 provides an external memory interface (emif) for connecting to external memory devices. the connection allows read and write accesses to external memories. the emif operates in conjunction with udbs, i/o ports, and other hardware to generate external memory address and control signals. figure 5-1 is the emif block diagram. the emif supports synchronous and asynchronous memories. the cy8c52 only supports one type of external memory device at a time. external memory is located in the cortex-m3 external ram space; it can use up to 24 address bits. see ?memory map? section on page 18. the memory can be 8 or 16 bits wide. cortex-m3 instructions can be fe tched/executed from external memory, although at a slower rate than from flash. table 5-1. flash protection protection setting allowed not allowed unprotected external read and write + internal read and write - factory upgrade external write + internal read and write external read field upgrade internal read and write external read and write full protection internal read external read and write + internal write [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 17 of 85 figure 5-1. emif block diagram phub io if udb emif io ports io ports io ports data, address, and control signals data, address, and control signals address signals data signals control signals data, address, and control signals em control signals other control signals dsi dynamic output control dsi to port control external_ mem_ data[15:0] external_ mem_ addr[23:0] [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 18 of 85 5.6 memory map the cortex-m3 has a fixed address map, which allows periph- erals to be accessed by simp le memory access instructions. 5.6.1 address map the 4 gb address space is divided into the ranges shown in ta b l e 5 - 2 : the bit-band feature allows individual bits in words in the bit-band region to be read or wr itten as atomic operations. this is done by reading or writing bit 0 of corresponding words in the bit-band alias region. for example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000c. to test the value of that bit, read addre ss 0x2200000c and the result is either 0 or 1 depending on the value of the bit. most memory accesses done by the cortex-m3 are aligned, that is, done on word (4-byte) boundary addresses. unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 5.6.2 address map and cortex-m3 buses the icode and dcode buses are used only for accesses within the code address range, 0 - 0x1fffffff. the system bus is used for data accesses and debug accesses within the ranges 0x20000000 - 0xdfffffff and 0xe0100000 - 0xffffffff. instruction fetches can also be done within the range 0x20000000 - 0x3fffffff, although these can be slower than instruction fetches via the icode bus. the private peripheral bus (ppb) is used within the cortex-m3 to access system control registers and debug and trace module registers. table 5-2. address map address range size use 0x00000000 ? 0x1fffffff 0.5 gb program code. this includes the exception vector table at power up, which starts at address 0. 0x20000000 ? 0x3fffffff 0.5 gb static ram. this includes a 1 mbyte bit-band region starting at 0x20000000 and a 32 mbyte bit-band alias region starting at 0x22000000. 0x40000000 ? 0x5fffffff 0.5 gb peripherals. this includes a 1 mbyte bit-band region starting at 0x40000000 and a 32 mbyte bit-band alias region starting at 0x42000000. 0x60000000 ? 0x9fffffff 1 gb external ram. 0xa0000000 ? 0xdfffffff 1 gb external peripherals. 0xe0000000 ? 0xffffffff 0.5 gb internal peripherals, including the nvic and debug and trace modules. table 5-3. peripheral data address map address range purpose 0x00000000 ? 0x0003ffff 256k flash 0x1fff8000 ? 0x1fffffff 32k sram in code region 0x20000000 ? 0x20007fff 32k sram in sram region 0x40004000 ? 0x400042ff clocking, plls, and oscillators 0x40004300 ? 0x400043ff power management 0x40004500 ? 0x400045ff ports interrupt control 0x40004700 ? 0x400047ff system performance controller 0x40004800 ? 0x400048ff cache controller 0x40004900 ? 0x400049ff i 2 c controller 0x40004e00 ? 0x40004eff decimator 0x40004f00 ? 0x40004fff fixed timer, counter, pwms 0x40005000 ? 0x400051ff general purpose i/os 0x40005300 ? 0x4000530f output port select register 0x40005400 ? 0x400054ff external memory interface (emif) control registers 0x40005800 ? 0x40005fff analog subsystem interface 0x40006000 ? 0x400060ff usb controller 0x40006400 ? 0x40006fff udb configuration 0x40007000 ? 0x40007fff phub configuration 0x40008000 ? 0x400087ff eeprom 0x4000a000 ? 0x4000a400 can 0x4000c000 ? 0x4000c800 digital filter block 0x40010000 ? 0x4001ffff digital interconnect configuration 0x60000000 ? 0x60ffffff external memory interface (emif) 0x80000000 ? 0x800007fff flash ecc bytes 0xe0000000 ? 0xe00fffff co rtex-m3 ppb registers, including nvic, debug, and trace table 5-3. peripheral data address map (continued) address range purpose [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 19 of 85 6. system integration 6.1 clocking system the clocking system generates, di vides, and distributes clocks throughout the psoc system. fo r the majority of systems, no external crystal is required. the imo and pll can generate up to a 40 mhz clock, accurate to 1% over voltage and temper- ature. additional internal and external clock sources allow each design to optimize accuracy, power, and cost. all of the system clock sources can be used to g enerate other clock frequencies in the 16-bit clock dividers and throughout the device for anything the user wants, for example a uart baud rate generator. clock generation and distribution is automatically configured through the psoc creator ide graphical interface. this is based on the complete system?s requirements. it greatly speeds the design process. psoc creator allows designers to build clocking systems with minimal input. the designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the re quired specifications. this is possible because of the programmability inherent psoc. key features of the clocking system include: ? seven general purpose clock sources ? 3 to 40 mhz imo 1% at 3 mhz ? 4 to 33 mhz external crystal oscillator (mhzeco) ? dsi signal from an external i/o pin or other logic ? 24 to 40 mhz fractional phas e-locked loop (pll) sourced from imo, mhzeco, or dsi ? clock doubler ? 1 khz, 33 khz, 100 khz ilo for watch dog timer (wdt) and sleep timer ? 32.768 khz external crystal oscillator (khzeco) for real time clock (rtc) ? 36 mhz fixed clock (available only during test mode) ? dedicated 48 mhz internal oscillator for usb that auto locks to usb bus clock requiring no external crystal for usb. (usb equipped parts only) ? independently sourced clock dividers in all clocks ? eight 16-bit clock dividers for the digital system ? four 16-bit clock dividers for the analog system ? dedicated 16-bit divider for the cpu bus and cpu clock ? automatic clock configuration in psoc creator table 6-1. oscillator summary source fmin tolerance at fmin fmax tolerance at fmax startup time imo 3 mhz 1% over voltage and temperature 40 mhz 5% 10 s max mhzeco 4 mhz crystal dependent 33 mhz crystal dependent 5 ms typ, max is crystal dependent dsi 0 mhz input dependent 33 mhz input dependent input dependent pll 24 mhz input dependent 40 mhz input dependent 250 s max doubler 12 mhz input dependent 48 mhz input dependent 1 s max ilo 1 khz -30%, +65% 100 khz -20%, +30% 1000 s max khzeco 32 khz crystal dependent 32 khz crystal dependent 500 ms typ, max is crystal dependent [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 20 of 85 figure 6-1. clocking subsystem 6.1.1 internal oscillators 6.1.1.1 internal main oscillator in most designs the imo is the only clock source required, due to its 1% accuracy. the imo o perates with no external compo- nents and outputs a stable clock. a factory trim for each frequency range is stored in the device. with the factory trim, tolerance varies from 1% at 3 mhz, up to 10% at 72 mhz. the imo, in conjunction with the pll, allows generation of up to a 66 mhz clock with 1% accuracy. the imo provides clock outputs at 3, 6, 12, 24, 48, and 72 mhz. 6.1.1.2 clock doubler the clock doubler outputs a clock at twice the frequency of the input clock. the doubler works for input frequency ranges of 6 to 24 mhz (providing 12 to 72 mhz at the output). it can be configured to use a clock from the imo, mhzeco, or the dsi (external pin). 6.1.1.3 phase-locked loop the pll allows low frequency, high accuracy clocks to be multi- plied to higher frequencies. this is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. the pll block provides a mechanism for generating clock frequencies based upon a variety of input sources. the pll outputs clock frequencies in the range of 24 to 40 mhz. its input and feedback dividers supply 4 032 discrete ratios to create almost any desired system clock frequency. the most common pll use is to multiply the imo cl ock at 3 mhz, where it is most accurate to generate the cpu and system clocks up to the device?s maximum frequency. the pll achieves phase lock within 250 s (verified by bit setting). it can be configured to use a clock from the imo, mhzeco, dsi (external pin), or doubler. the pll clock source can be used until lock is complete and signaled with a lock bit. disable the pll before entering low power modes. 6.1.1.4 internal low speed oscillator the ilo provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. the ilo generates up to three different clocks: 1 khz, 33 khz, and 100 khz. the 1 khz clock (clk1k) is typically used for a background ?heartbeat? timer. this clock inhe rently lends itself to low power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (ctw). the central timewheel is a 1 khz, free running, 13-bit counter clocked by the ilo. the central timewheel is always enabled except in hibernate mode and when the cpu is stopped during debug on chip mode. it can be used to generate periodic inter- rupts for timing purposes or to wake the system from a low power mode. firmware can reset the central timewheel. 4-33 mhz eco 3-72 mhz imo 32 khz eco 1,33,100 khz ilo s k e w 7 7 digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit analog clock divider 16 bit bus/cpu clock divider 16 bit 12-72 mhz doubler 24-40 mhz pll system clock mux external io or dsi 0-33 mhz s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 21 of 85 the central timewhee l can be programmed to wake the system periodically and optionally issue an interrupt. this enables flexible, periodic wakeups from low power modes or coarse timing applications. systems that require accurate timing should use the real time clock capability instead of the central timewheel. the 100 khz clock (clk100k) works as a low power system clock to run the cpu. it can also generate time intervals such as fast sleep intervals using the fast timewheel. the fast timewheel is a 100 khz, 5-bit counter clocked by the ilo that can also be used to wake the system. the fast timewheel settings are programmable, and th e counter automatically resets when the terminal count is reached. this enables flexible, periodic wakeups of the cpu at a higher rate than is allowed using the central timewheel. the fast timewheel can generate an optional interrupt each time the terminal count is reached. the 33 khz clock (clk33k) comes from a divide-by-3 operation on clk100k. this output can be used as a reduced accuracy version of the 32.768 khz eco clock with no need for a crystal. 6.1.2 external oscillators 6.1.2.5 mhz external crystal oscillator the mhzeco provides high frequency, high precision clocking using an external crystal. it supports a wide variety of crystal types, in the range of 4 to 33 mhz. when used in conjunction with the pll, it can synthesize a wide range of precise clock frequencies up to 40 mhz. the gpio pins connecting to the external crystal and capacitors are fixed. mhzeco accuracy depends on the crystal chosen. 6.1.2.6 digital system interconnect the dsi provides rout ing for clocks taken from external clock oscillators connected to i/o. the oscillators can also be generated within the device in the digital system and universal digital blocks. while the primary dsi clock input provides access to all clocking resources, up to eight other ds i clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. this is only possible if there are multiple precision clock sources. 6.1.2.7 32.768 khz eco the 32.768 khz external crystal oscillator (32khzeco) provides precision timing with minimal power consumption using an external 32.768 khz wa tch crystal. the 32khzeco also connects directly to the sleep timer and provides the source for the real time clock (rtc). the rtc uses a 1 second interrupt to implement the rtc func tionality in firmware. the oscillator works in two distinct power modes. this allows users to trade off power consumption with noise immunity from neighboring circuits. the gpio pins connected to the external crystal and capacitors are fixed. 6.1.3 clock distribution all seven clock sources are inputs to the central clock distribution system. the distribution system is designed to create multiple high precision clocks. these clocks are customized for the design?s requirements and el iminate the common problems found with limited resolution prescalers attached to peripherals. the clock distribution system ge nerates several types of clock trees. ? the system clock is used to s elect and supply the fastest clock in the system for general system clock requirements and clock synchronization of the psoc device. ? bus clock 16-bit divider uses th e system clock to generate the system?s bus clock used for data transfers and the cpu. the cpu clock is directly derived from the bus clock. ? eight fully programmable 16-bit clock dividers generate digital system clocks for general us e in the digital system, as configured by the design?s requirements. digital system clocks can generate custom clocks de rived from any of the seven clock sources for any purpose. examples include baud rate generators, accurate pwm periods, and timer clocks, and many others. if more than eight digital clock dividers are required, the universal digital bloc ks (udbs) and fixed function timer/counter/pwms can also generate clocks. ? four 16-bit clock dividers gener ate clocks for the analog system components that require clocking, such as the adc. the analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. this is done to reduce analog system noise. each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. the outputs from each di gital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 usb clock domain the usb clock domain is unique in that it operates largely asynchronously from the ma in clock network. the usb logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process usb data. the usb logic requires a 48 mhz frequency. this frequency can be generated from different sources, including dsi clock at 48 mhz or doubled value of 24 mhz from internal osci llator, dsi signal, or crystal oscillator. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 22 of 85 6.2 power system the power system consists of sepa rate analog, digital, a nd i/o supply pins, label ed vdda, vddd, and vddiox, resp ectively. it al so includes two internal 1.8v regulators that provide the digital (v ccd) and analog (vcca) supplies for the internal core logic. t he output pins of the regulators (vccd and vcca) and the vddio pins must have capacitors connected as shown in figure 6-2 . one of the vccd pins must have a 1 f 10% x5r capacitor connected to vssd. the other vccd pin should have a 0.1 f 10% x5r capacitor connected to vssd. also, a trace that is as short as possible must run between the two vccd pins. the power system also contain s a sleep regulator, an i 2 c regulator, and a hibernate regulator. figure 6-2. psoc power system 6.2.1 power modes psoc 5 devices have four different power modes. the power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. psoc 5 power modes, in order of decreasing power consumption are: ? active ? alternate active ? sleep ? hibernate active is the main processing m ode. its functionality is config- urable. each power controllable subsystem is enabled or disabled by using separate power configuration template registers. in alternate active mode, fewer subsystems are enabled, reducing power. in sleep mode most resources are disabled regardless of the temp late settings. sleep mode is optimized to provide timed sleep intervals and real time clock functionality. the lowest power mode is hibernate, which retains register and sram state, but no clocks, and allows wakeup only from i/o pins. figure 6-3 illustrates the allowable transitions between power modes. vssd vssd vddio1 vddio2 vddio0 vddio3 vccd vddd vssd vccd vddd vssa vcca vdda digital regulators analog regulator analog domain digital domain i2c regulator sleep regulator hibernate regulator i/ o supply i/ o supply i/o supply i/o supply . vddio2 vddio0 vddio3 vddio1 0.1 f 0.1 f 0.1 f 0.1 f vddd vddd vdda 1 f 1 f 0.1 f [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 23 of 85 figure 6-3. power mode transitions 6.2.1.1 active mode active mode is the primary operating mode of the device. when in active mode, the active configuration template bits control which available resources are enabled or disabled. when a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. user firmware c an dynamically control subsystem power by setting and clearing bits in the active configuration template. the cpu can disable itself, in which case the cpu is automatically reenabled at the next wakeup event. when a wakeup event occurs, the global mode is always returned to active, and the cpu is automatically enabled, regardless of its template settings . active mode is the default global power mode upon boot. table 6-2. power modes power modes description entry condition wakeup source active clocks regulator active primary mode of operation, all peripherals available (program- mable) wakeup, reset, manual register entry any interrupt any (program- mable) all regulators available. digital and analog regulators can be disabled if external regulation used. alternate active similar to active mode, and is typically configured to have fewer peripherals active to reduce power. one possible configuration is to turn off the cpu and flash, and run periph- erals at full speed manual register entry any interrupt any (program- mable) all regulators available. digital and analog regulators can be disabled if external regulation used. sleep all subsystems automatically disabled manual register entry picu, comparator, i 2 c, rtc, ctw, xres_n, wdr, ppor, hbr ilo/eco32k both digital and analog regulators buzzed. digital and analog regulators can be disabled if external regulation used. hibernate all subsys tems automatically disabled lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled configuration and memory contents retained manual register entry picu, xres_n, hbr only hibernate regulator active. table 6-3. power modes wakeup time and power consumption sleep modes wakeup time power (typ) code execution digital resources analog resources clock sources available wakeup sources reset sources active - 2 ma [5] yes all all all - all alternate active - 20 a user defined all all all - all sleep <12 s 2 a no i 2 c comparator ilo/khzeco picu, comparator, i 2 c, rtc, ctw xres, lvd, wdr hibernate <100 s 300 na no none none none picu xres, hres note 5. imo 6 mhz, cpu 6 mhz, all peripherals disabled. active alternate active hibernate sleep [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 24 of 85 6.2.1.2 alternate active mode alternate active mode is very similar to ac tive mode. in alternate active mode, fewer subsystems are enabled, to reduce power consumption. one possible confi guration is to turn off the cpu and flash, and run peripherals at full speed. 6.2.1.3 sleep mode sleep mode reduces power consum ption when a resume time of 12 s is acceptable. the wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode. 6.2.1.4 hibernate mode in hibernate mode nearly all of the internal functions are disabled. internal voltages are reduced to the minimal level to keep vital systems alive. confi guration state is preserved in hibernate mode and sram memory is retained. gpios configured as digital outputs maintain their previous values and external gpio pin interrupt settings are preserved. the hibernate reset (hres) occurs if the internal voltage falls below the minimum level required for state retention. the device can only return from hibernate mode in response to an external i/o interrupt. the resume time from hibernate mode is less than 100 s. 6.2.1.5 wakeup events wakeup events are configurable and can come from an interrupt or device reset. a wakeup event restores the system to active mode. interrupt sources include internally generated interrupts, power supervisor, cent ral timewheel, and i/o interrupts. internal interrupt sources can come from a variety of peripherals, such as analog comparators and udbs. the central timewheel provides periodic interrupts to al low the system to wake up, poll peripherals, or perform real-tim e functions. reset event sources include the external reset i/o pin (xres), wdt, and precision reset (pres). 6.2.2 boost converter applications that use a supply voltage of less than 1.71v, such as solar or single cell battery supplies, may use the on-chip boost converter. the boost converter may also be used in any system that requires a higher operating voltage than the supply provides. for instance, this includes driving 5.0v lcd glass in a 3.3v system. the boost converter acce pts an input voltage as low as 0.5v. with one low cost inductor it produces a selectable output voltage sourcing enough current to operate the psoc and other on-board components. the boost converter accepts an input voltage from 0.5v to 5.5v (vbat). the converter provides a user configurable output voltage of 1.8 to 5.0v (vboost); vbat must be less than vboost. the block can deliver up to 50 ma (iboost) depending on config- uration. four pins are associated with the boost converter: vbat, vssb, vboost, and ind. the boosted output voltage is sensed at the vboost pin and must be connected directly to the chip?s supply inputs. an inductor is connect ed between the vbat and ind pins. the designer can optimize the inductor value to increase the boost converter efficiency based on input voltage, output voltage, current and switching frequency. the external schottky diode shown in figure 6-4 is required only in cases when vboost>3.6v. figure 6-4. application for boost converter the boost converter can be operated in two different modes: active and standby. active mode is the normal mode of operation where the boost regulator actively generates a regulated output voltage. in standby mode, most boost functions are disabled, thus reducing power consumption of the boost circuit. the converter can be configured to provide low power, low current regulation in the standby mode. the external 32 khz crystal can be used to generate inductor boost pulses on the rising and falling edge of the clock when the output voltage is less than the programmed value. this is called automatic thump mode (atm). the boost typically draws 200 a in active mode and 12 a in standby mode. the boost operating modes must be used in conjunction with chip power modes to minimize the total chip power consumption. table 6-4 lists the boost power modes available in different chip power modes. the switching frequency can be set to 100 khz, 400 khz, 2 mhz, or 32 khz to optimize efficiency and component cost. the 100 khz, 400 khz, and 2 mhz switching frequencies are generated using oscillators internal to the boost converter block. when the 32 khz switching frequency is s elected, the clock is derived from a 32 khz external crystal oscillator. the 32 khz external clock is primarily intended for boost standby mode. if the boost converter is not used in a given application, tie the vbat, vssb, and vboost pins to ground and leave the ind pin unconnected. table 6-4. chip and boost power modes compatibility chip power modes boost power modes chip -active mode boost can be operated in either active or standby mode. chip -sleep mode boost can be operated in either active or standby mode. however, it is recom- mended to operate boost in standby mode for low power consumption chip-hibernate mode boost can only be operated in active mode. however, it is recommended not to use boost in chip hibernate mode due to high current consumption in boost active mode psoc vboost ind vbat vssb vssd vdda vddd vssa 22 f 0. 1 f 22 f 10 h optional schottky diode only required vboost > 3.6v vddio smp [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 25 of 85 6.3 reset cy8c52 has multiple internal and external reset sources available. the reset sources are: ? power source monitoring - the analog and digital power voltages, vdda, vddd, vcca, and vccd are monitored in several different modes during power up, normal operation, and sleep and hibernate states. if any of the voltages goes outside prede- termined ranges then a reset is generated. the monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. ? external - the device can be rese t from an external source by pulling the reset pin (xres) low. the xres pin includes an internal pull up to vddio1. vddd, vdda, and vddio1 must all have voltage applied before the part comes out of reset. ? watchdog timer - a watchdog timer monitors the execution of instructions by the processor. if the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset. ? software - the device can be reset under program control. figure 6-5. resets the term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. a reset status register holds the source of the most recent reset or power voltage monitoring interrupt. the program may examine this register to detect and report exception conditions. this register is cleared after a power on reset. 6.3.1 reset sources 6.3.1.1 power voltage level monitors ? ipor - initial power on reset at initial power on, ipor monitors the power voltages vddd and vdda, both directly at the pins and at the outputs of the corresponding internal regulators. the trip level is not precise. it is set to a voltage below th e lowest specifie d operating volt- age but high enough for the internal circuits to be reset and to hold their reset state. the monitor generates a reset pulse that is at least 100 ns wide. it may be much wider if one or more of the voltages ramps up slowly. to save power the ipor circuit is disabled when the internal digital supply is stable. voltage supervision is then handed off to the precise low voltage reset (pres) circuit. when the volt- age is high enough for pres to release, the imo starts. reset controller watchdog timer external reset power voltage level monitors software reset register vddd vdda reset pin system reset processor interrupt [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 26 of 85 ? pres - precise low voltage reset this circuit monitors the outputs of the analog and digital inter- nal regulators after power up. the regulator outputs are com- pared to a precise reference voltage of 1.6v 0.02v. the re- sponse to a pres trip is identical to an ipor reset. in normal operating mode, the program cannot disable the dig- ital pres circuit. the analog regulator can be disabled, which also disables the analog portion of the pres. the pres cir- cuit is disabled automatically during sleep and hibernate modes, with one exception: during sleep mode the regulators are periodically activated (buzz ed) to provide supervisory ser- vices and to reduce wakeup time. at these times the pres circuit is also buzzed to allow periodic voltage monitoring. ? hres - hibernate/sleep low voltage reset this circuit monitors internal vo ltage and issues a reset if the voltage drops below a point where state information may be lost. the response to a hres trip is identical to an ipor reset. this circuit is ultra low power. it is enabled at all times but its output only causes a reset when the device is in hibernate or sleep mode. ? alvi, dlvi, ahvi - analog/digital low voltage interrupt, analog high voltage interrupt interrupt circuits are available to detect when vdda and vddd go outside a voltage range. for ahvi, vdda is compared to a fixed trip level. for alvi and dlvi, vdda and vddd are com- pared to trip levels that are programmable, as listed in table 6-5 . the monitors are disabled until after ipor. during sleep mode these circuits are periodically activated (buzzed). if an interrupt occurs during buzzing then the system first enters its wakeup sequence. the interrupt is then recognized and may be ser- viced. 6.3.1.2 other reset sources ? xres - external reset cy8c52 has either a single gpio pin that is configured as an external reset or a dedicated xres pin. either the dedicated xres pin or the gpio pin, if configured, holds the part in reset while held active (low). the response to an xres is the same as to an ipor reset. the external reset is active low. it includes an internal pull up resistor. xres is active during sleep and hibernate modes. ? sres - software reset a reset can be commanded under program control by setting a bit in the software reset register. this is done either directly by the program or indirectly by dma access. the response to a sres is the same as after an ipor reset. another register bit exists to disable this function. ? wres - watchdog timer reset the watchdog reset detects when the software program is no longer being executed correctly. to indicate to the watchdog timer that it is running correct ly, the program must periodically reset the timer. if th e timer is not reset be fore a user-specified amount of time, then a reset is generated. note ipor disables the watchdo g function. the program must enable the watchdog function at an appropriate point in the code by setting a register bit. w hen this bit is set, it cannot be cleared again except by an ipor power on reset event. 6.4 i/o system and routing psoc i/os are extremely flexible. every gpio has analog and digital i/o capability. all i/os have a large number of drive modes, which are set at por. psoc also provides up to four individual i/o voltage domains through the vddio pins. there are two types of i/o pins on every device; those with usb provide a third type. both general purpose i/o (gpio) and special i/o (sio) provide similar di gital functionality. the primary differences are their analog capability and drive strength. devices that include usb also provide two usbio pins that support specific usb functionality as well as limited gpio capability. all i/o pins are available for use as digital inputs and outputs for both the cpu and digital peripherals. in addition, all i/o pins can generate an interrupt. the flexible and advanced capabilities of the psoc i/o, combined with any signal to any pin routability, greatly simplify circuit design and board layout. all gpio pins can be used for analog input, capsense [4] , and lcd segment drive, while sio pins are used for voltage s in excess of vdda and for programmable output voltages. ? features supported by both gpio and sio: ? user programmable port reset state ? separate i/o supplies and voltages for up to four groups of i/o ? digital peripherals use dsi to connect the pins ? input or output or both for cpu and dma ? eight drive modes ? every pin can be an interrupt source configured as rising edge, falling edge or both edges. if required, level sensitive interrupts are supported through the dsi ? dedicated port interrupt vector for each port table 6-5. analog/digital low voltage interrupt, analog high voltage interrupt interrupt supply normal voltage range available trip settings accuracy dlvi vddd 1.71v-5.5v 1.70v-5.45v in 250 mv increments 2% alvi vdda 1.71v-5.5v 1.70v-5.45v in 250 mv increments 2% ahvi vdda 1.71v-5.5v 5.75v 2% [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 27 of 85 ? slew rate controlled digital output drive mode ? access port control and configuration registers on either port basis or pin basis ? separate port read (ps) and write (dr) data registers to avoid read modify write errors ? special functionality on a pin by pin basis ? additional features only provided on the gpio pins: ? lcd segment drive on lcd equipped devices ? capsense on capsense equipped devices [4] ? analog input and output capability ? continuous 100 a clamp current capability ? standard drive strength down to 1.71v ? additional features only provided on sio pins: ? higher drive strength than gpio ? hot swap capability (5v tolerance at any operating vdd) ? programmable and regulated high input and output drive levels down to 1.2v ? no analog input or lcd capability ? over voltage tolerance up to 5.5v ? sio can act as a general purpose analog comparator ? usbio features: ? full speed usb 2.0 compliant i/o ? highest drive strength for general purpose use ? input, output, or both for cpu and dma ? input, output, or both for digital peripherals ? digital output (cmos) drive mode ? each pin can be an interrupt source configured as rising edge, falling edge, or both edges [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 28 of 85 figure 6-6. gpio block diagram drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw lcd logic & mux prt[x]dm1 prt[x]dm2 prt[x]lcd_en prt[x]lcd_com_seg analog analog mux enable analog global enable digital system output 0 1 prt[x]byp prt[x]bie bidirectional control capsense global control switches pin interrupt signal digital system input prt[x]ps prt[x]ctl input buffer disable display data interrupt logic picu[x]inttype[y] picu[x]intstat vio vio vio slew cntl lcd bias bus 5 prt[x]amux prt[x]ag 1 caps[x]cfg1 oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat naming convention ?x? = port number ?y? = pin number 0 1 0 1 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 29 of 85 figure 6-7. sio input/output block diagram figure 6-8. usbio block diagram drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw prt[x]dm1 prt[x]dm2 digital system output 0 1 prt[x]byp prt[x]bie bidirectional control pin interrupt signal digital system input prt[x]ps input buffer disable interrupt logic picu[x]inttype[y] picu[x]intstat slew cntl oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat prt[x]sio_diff buffer thresholds driver vhigh prt[x]sio_cfg prt[x]sio_hyst_en naming convention ?x? = port number ?y? = pin number reference level reference level drive logic usbio_cr1[4,5] pin digital output path digital input path digital system output 0 1 prt[x]byp pin interrupt signal digital system input usbio_cr1[0,1] interrupt logic picu[x]inttype[y] picu[x]intstat in prt[x]dbl_sync_in picu[x]intstat naming convention ?x? = port number ?y? = pin number vio vio vio 5k 1.5k d+ pin only usbio_cr1[2] usbio_cr1[3] usbio_cr1[6] usbio_cr1[7] usb or i/o d+ 1.5k d+d- 5k open drain prt[x]sync_out usb sie control for usb mode usb receiver circuitry 3.3v [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 30 of 85 6.4.1 drive modes each gpio and sio pin is individually configurable into one of the eight drive modes listed in ta b l e 6 - 6 . three configuration bits are used for each pin (dm[2:0]) and set in the prtxdm[2:0] registers. figure 6-9 depicts a simplified pin view based on each of the eight drive modes. table 6-6 shows the i/o pin?s drive state based on the port data register value or digital array signal if bypass mode is selected. note t hat the actual i/o pin voltage is determined by a combination of the selected drive mode and the load at the pin. for example, if a gpio pin is configured for resistive pull up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. if the same gpio pin is externally tied to ground then the voltage unmea- sured at the pin is a low logic state. figure 6-9. drive mode ? high impedance analog the default reset state with both the output driver and digital input buffer turned off. this prevents any current from flowing in the i/o?s digital input buffer due to a floating voltage. this state is recommended for pins that are floating or that support an analog voltage. high impedance analog pins do not provide digital input functionality. to achieve the lowest chip current in sleep modes, all i/os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the psoc device or by external circuitry. ? high impedance digital the input buffer is enabled for digital signal input. this is the standard high impedance (hiz) state recommended for digital inputs. ? resistive pull up or resistive pull down resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the table 6-6. drive modes diagram drive mode prtxdm2 prtxdm1 prtxdm0 prtxdr = 1 prtxdr = 0 0 high impedence analog 0 0 0 high-z high-z 1 high impedance digital 0 0 1 high-z high-z 2 resistive pull up 0 1 0 res high (5k) strong low 3 resistive pull down 0 1 1 strong high res low (5k) 4 open drain, drives low 1 0 0 high-z strong low 5 open drain, drive high 1 0 1 strong high high-z 6 strong drive 1 1 0 strong high strong low 7 resistive pull up and pull down 1 1 1 res high (5k) res low (5k) high impedance analog ps dr ps dr ps dr 0. high impedance digital 1. resistive pull up 2. resistive pull down 3. open drain , drives low 4. open drain , drives high 5. strong drive 6. resistive pull up and down 7. vio pin pin pin vio pin vio pin vio pin vio pin pin ps dr ps dr ps dr ps dr ps dr [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 31 of 85 other. pins can be used for di gital input and output in these modes. interfacing to mechanical switches is a common appli- cation for these modes. ? open drain, drives high and open drain, drives low open drain modes provide high impedance in one of the data states and strong drive in the other. pins can be used for digital input and output in these modes. a common application for these modes is driving the i 2 c bus signal lines. ? strong drive provides a strong cmos output drive in either high or low state. this is the standard out put mode for pins. strong drive mode pins must not be used as inputs under normal circum- stances. this mode is often used to drive digital output signals or external fets. ? resistive pull up and pull down similar to the resistive pull up and resistive pull down modes except the pin is always in series with a resistor. the high data state is pull up while the low data state is pull down. this mode is most often used when othe r signals that may cause shorts can drive the bus. 6.4.2 pin registers registers to configure and interact with pins come in two forms that may be used interchangeably. all i/o registers are available in the standard port form, where each bit of the register corresponds to one of the port pins. this register form is efficient for quickly reconfiguring multiple port pins at the same time. i/o registers are also available in pin form, which combines the eight most commonly used port regi ster bits into a single register for each pin. this enables very fast configuration changes to individual pins with a single register write. 6.4.3 bidirectional mode high speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode such as strong drive (set using prtxdm[2:0] registers) for out put signals on the same pin, based on the state of an auxiliary control bus signal. the bidirec- tional capability is useful for processor busses and communica- tions interfaces such as the spi slave miso pin that requires dynamic hardware control of the output buffer. the auxiliary control bus routes up to 16 udb or digital peripheral generated output enable signals to one or more pins. 6.4.4 slew rate limited mode gpio and sio pins have fast and slow output slew rate options for strong and open drain drive modes, not resistive drive modes. because it results in reduced emi, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 mhz. the fast slew rate is for signals between 1 mhz and 33 mhz. the slew rate is individually configurable for each pin, and is set by the prtxslw registers. 6.4.5 pin interrupts all gpio and sio pins are able to generate interrupts to the system. all eight pins in each port interface to their own port interrupt control unit (picu) and associated interrupt vector. each pin of the port is independent ly configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to ?1? and an interrupt request is sent to the interrupt controller. each picu has its own interrupt vector in the interrupt controller and the pin status register providing easy determination of the interrupt source down to the pin level. port pin interrupts remain active in all sleep modes allowing the psoc device to wake from an externally generated interrupt. while level sensitive interrupts are not directly supported; universal digital blocks (udb) provide this functionality to the system when needed. 6.4.6 input buffer mode gpio and sio input buffers can be configured at the port level for the default cmos input thresholds or the optional lvttl input thresholds. all input buffers incorporate schmitt triggers for input hysteresis. additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 i/o power supplies up to four i/o pin power supplies are provided depending on the device and package. each i/o supply must be less than or equal to the voltage on the chip?s analog (vdda) pin. this feature allows users to provide different i/o volt age levels for different pins on the device. refer to the specific device package pinout to determine vddio capability for a given port and pin. the sio port pins support an additional regulated high output capability, as described in adjustable output level . 6.4.8 analog connections these connections apply only to gpio pins. all gpio pins may be used as analog inputs or outputs. the analog voltage present on the pin must not exceed the vddio supply voltage to which the gpio belongs. each gpio may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as adc or comparators. 6.4.9 capsense this section applies only to gpio pins. all gpio pins may be used to create capsense buttons and sliders [4] . see the ?capsense? section on page 50 for more information. 6.4.10 lcd segment drive this section applies only to gpio pins. all gpio pins may be used to generate segment and common drive signals for direct glass drive of lcd glass. see the ?lcd direct drive? section on page 49 for details. 6.4.11 adjustable output level this section applies only to sio pins. sio port pins support the ability to provide a regulated hi gh output level for interface to external signals that are lower in voltage than the sio?s respective vddio. sio pins are individually configurable to output either the standard vddio level or the regulated output, which is based on an internally generated reference. typically, an [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 32 of 85 external voltage routed through an extref pin is used to generate the reference. 6.4.12 adjustable input level this section applies only to sio pins. sio pins by default support the standard cmos and lvttl input levels but also support a differential mode with prog rammable levels. sio pins are grouped into pairs. each pair shares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from vddio. the reference sets the pins voltage threshold for a high logic level. available input thresholds are: ? 0.5 vddio ? 0.4 vddio ? 0.5 vref ? vref typically, an external voltage routed through an extref pin generates the vref reference. 6.4.13 sio as comparator this section applies only to sio pins. the adjustable input level feature of the sios as explained in the adjustable input level section can be used to construct a comparator. the threshold for the comparator is provided by th e sio's reference generator. the reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. note that a pair of sio pins share the same threshold. the digital input path in figure 6-7 on page 29 illustrates this functionality. in the figure, ?reference level? is the analog signal routed through the analog global. the hysteresis feature can also be enabled for the input buffer of the sio, which increases noise immunity for the comparator. 6.4.14 hot swap this section applies only to sio pins. sio pins support ?hot swap? capability to plug into an application without loading the signals that are connected to the sio pins even when no power is applied to the psoc device. this allows the unpowered psoc to maintain a high impedance load to the external device while also preventing the psoc from being powered through a gpio pin?s protection diode. 6.4.15 over voltage tolerance all i/o pins provide an over voltage (vddio < vin < vdda) tolerance feature at any operating vdd. ? there are no current limitations for the sio pins as they present a high impedance load to the external circuit. ? the gpio pins must be limited to 100 a using a current limiting resistor. gpio pins clamp the pin voltage to approximately one diode above the vddio supply. ? in case of a gpio pin configured for analog input/output, the analog voltage on the pin must not exceed the vddio supply voltage to which the gpio belongs. a common application for this feature is connection to a bus such as i 2 c where different devices are running from different supply voltages. in the i 2 c case, the psoc chip is configured into the open drain, drives low mode for the sio pin. this allows an external pull up to pull the i 2 c bus voltage above the psoc pin supply. for example, the psoc chip could operate at 1.8v, and an external device could run from 5v. note that the sio pin?s vih and vil levels are determined by the associated vddio supply pin. the i/o pin must be configur ed into a high impedance drive mode, open drain low drive mode, or pull down drive mode, for over voltage tolerance to work properly. absolute maximum ratings for the device must be observed for all i/o pins. 6.4.16 reset configuration by default all i/os reset to the high impedance analog state but are reprogrammable on a port-by-port basis. they can be reset as high impedance analog, pull down, or pull up, based on the application?s requirements. to ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. the stored reset data is automatically transferred to the port reset configuration registers at ppor release. 6.4.17 low power functionality in all low power modes the i/o pins retain their state until the part is awakened and changed or reset. to awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low power modes. 6.4.18 special pin functionality some pins on the device include additional special functionality in addition to their gpio or sio functionality. the specific special function pins are listed in ?pinouts? on page 5. the special features are: ? digital ? 4 to 33 mhz crystal oscillator ? 32.768 khz crystal oscillator ? wake from sleep on i 2 c address match. any pin can be used for i 2 c if wake from sleep is not required. ? jtag interface pins ? swd interface pins ? swv interface pins ? external reset ? analog ? external reference inputs 6.4.19 jtag boundary scan the device supports standard jtag boundary scan chains on all pins for board level test. 7. digital subsystem the digital programmable system creates application specific combinations of both standard and advanced digital peripherals and custom logic functions. thes e peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and ip security. the features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. designers do not need to interact directly with the programmable digital system at the hardware and register level. psoc creator [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 33 of 85 provides a high level schematic capture graphical interface to automatically place and route resources similar to plds. the main components of the digital programmable system are: ? universal digital blocks (udb) - these form the core function- ality of the digital programmab le system. udbs are a collection of uncommitted logic (pld) and structural logic (datapath) optimized to create all co mmon embedded peripherals and customized functionality that are application or design specific. ? universal digital block array - udb blocks are arrayed within a matrix of programmable interconnect. the udb array structure is homogeneous and allows for flexible mapping of digital functions onto the array. the array supports extensive and flexible routing interconnects between udbs and the digital system interconnect. ? digital system interconnect (d si) - digital signals from universal digital blocks (udbs), fixed function pe ripherals, i/o pins, interrupts, dma, and ot her system core signals are attached to the digital system interconnect to implement full featured device connectivity. the dsi allows any digital function to any pin or other feature routability when used with the universal digital block array. figure 7-1. cy8c52 digital programmable architecture 7.1 example peripherals the flexibility of the cy8c52 family?s universal digital blocks (udbs) and analog blocks allow the user to create a wide range of components (peripherals). the most common peripherals were built and characterized by cypress and are shown in the psoc creator component catalog, however, users may also create their own custom components using psoc creator. using psoc creator, users may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. the number of components available through psoc creator is too numerous to list in the data sheet, and the list is always growing. an example of a component available for use in cy8c52 family, but, not explicitly called out in this data sheet is the uart component. io port digital core system and fixed function peripherals udb array udb array io port io port io port dsi routing interface dsi routing interface digital core system and fixed function peripherals udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 34 of 85 7.1.1 example digital components the following is a sample of the digital components available in psoc creator for the cy8c52 family. the exact amount of hardware resources (udbs, rout ing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? communications ? i 2 c (1 to 3 udbs) ? uart (1 to 3 udbs) ? functions ? emif (external memory interface, 1 udb) ? logic (x cpld product terms per logic function) ? not ? or ? xor ? and 7.1.2 example analog components the following is a sample of the analog components available in psoc creator for the cy8c52 family. the exact amount of hardware resources (s c/ct blocks, routing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? adc ? successive approximation (sar) ? comparators 7.1.3 example system function components the following is a sample of the system function components available in psoc creator for the cy8c52 family. the exact amount of hardware resources (udbs, routing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? capsense ? lcd drive ? lcd control ? filters 7.1.4 designing with psoc creator 7.1.4.1 more than a typical ide a successful design tool allows for the rapid development and deployment of both simple and complex designs. it reduces or eliminates any learning curve. it makes the integration of a new design into the production stream straightforward. psoc creator is that design tool. psoc creator is a full feat ured integrated development environment (ide) for hardware and software design. it is optimized specifically for psoc devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. this unique combination of tools makes psoc creator the most flexible embedded design platform available. graphical design entry simplifies the task of configuring a particular part. you can select t he required functionality from an extensive catalog of components and place it in your design. all [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 35 of 85 psoc creator automatically configures clocks and routes the i/o to the selected pins and then generates apis to give the appli- cation complete control over the hardware. changing the psoc device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. at any stage of development you are free to change the hardware configuration and even the target processor. to retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. you also have the ability to change the c compiler and evaluate an alternative. components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. switching co mpilers is as easy as editing the from the project options and rebuilding the application with no errors from the generated apis or boot code. figure 7-2. psoc creator framework [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 36 of 85 7.1.4.2 component catalog figure 7-3. component catalog the component catalog is a repository of reusable design elements that select device functionality and customize your psoc device. it is populated with an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and pwms, plus analog components such as adc and communication protocols, such as i 2 c, usb and can. see ?example peripherals? section on page 33 for more details about available peripherals. all content is fully characterize d and carefully documented in datasheets with code examples, ac/dc specifications, and user code ready apis. 7.1.4.3 design reuse the symbol editor gives you the ability to develop reusable components that can significantly reduce future design time. just draw a symbol and associate that symbol with your proven design. psoc creator allows for the placement of the new symbol anywhere in the component catalog along with the content provided by cypress. y ou can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit the details of the implementation. 7.1.4.4 software development figure 7-4. code editor anchoring the tool is a moder n, highly customizable user interface. it includes project ma nagement and int egrated editors for c and assembler source code, as well the design entry tools. project build control leverages compiler technology from top commercial vendors such as arm? limited, keil?, and codesourcery (gnu). free versions of keil c51 and gnu c compiler (gcc) for arm, with no restrictions on code size or end product distribution, are included with the tool distribution. upgrading to more optimizing compilers is a snap with support for the professional keil c51 product and arm realview? compiler. 7.1.4.5 nonintrusive debugging figure 7-5. psoc creator debugger with jtag (4-wire) and swd (2-wire) debug connectivity available on all devices, the ps oc creator debugger offers full control over the target device with minimum intrusion. break- points and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows?register, locals, watch, call stack, memory and periph- erals?make for an unparalleled level of visibility into the system. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 37 of 85 psoc creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. all steps of the design fl ow are carefully integrated and optimized for ease-of-use and to maximize productivity. 7.2 universal digital block the universal digital block (udb) represents an evolutionary step to the next generation of psoc embedded digital peripheral functionality. the architecture in first generation psoc digital blocks provides coarse progra mmability in which a few fixed functions with a small number of options are available. the new udb architecture is the optim al balance between configuration granularity and efficient implementation. a cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. to achieve this, udbs consist of a combination of uncommitted logic (pld), structured logic (datapath), and a flexible routing scheme to provide interconnect between these elements, i/o connections, and other peripherals. udb functionality ranges from simple self contained functi ons that are implemented in one udb, or even a portion of a udb (unused resources are available for other functions), to more complex functions that require multiple udbs. examples of basic functions are timers, counters, crc generators, pwms, dead band generators, and communications functions, such as uarts, spi, and i 2 c. also, the pld blocks and connectivity provide full featured general purpose programmable logic within the limits of the available resources. figure 7-6. udb block diagram the main component blocks of the udb are: ? pld blocks - there are two small plds per udb. these blocks take inputs from the routing array and form registered or combi- national sum-of-products logic. plds are used to implement state machines, state bits, and combinational logic equations. pld configuration is automatical ly generated from graphical primitives. ? datapath module - this 8-bit wide datapath contains structured logic to implement a dynamically configurable alu, a variety of compare configurations and condition generation. this block also contains input/output fifos, which are the primary parallel data interface between the cpu/dma system and the udb. ? status and control module - the primary role of this block is to provide a way for cpu firmware to interact and synchronize with udb operation. ? clock and reset module - this block provides the udb clocks and reset selection and control. 7.2.1 pld module the primary purpose of the pl d blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. in the simplest use model, consider the pld blocks as a standalone resource onto which general purpose rtl is synthesized and mapped. the more common and efficient use model is to create digital functions from a combination of pld and datapath blocks, where the pld implements only the random logic and state portion of the function while the datapath (alu) implements the more structured elements. figure 7-7. pld 12c4 structure one 12c4 pld block is shown in figure 7-7 . this pld has 12 inputs, which feed across eight product terms. each product term (and function) can be from 1 to 12 inputs wide, and in a given product term, the true (t) or complement (c) of each input can be selected. the product terms are summed (or function) to create the pld outputs. a sum can be from 1 to 8 product terms wide. the 'c' in 12c4 indicates that the width of the or gate (in this case 8) is constant acro ss all outputs (rather than variable as in a 22v10 device). this pla like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. there are two 12c4 plds in each udb. pld 12c4 (8 pts) pld 12c4 (8 pts) datapath clock and reset control routing channel datapath chaining pld chaining status and control pt0 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc pt1 pt2 pt3 pt4 pt5 pt6 pt7 tttttttt tttttttt tttttttt tttttttt and array or array mc0 mc1 mc2 out0 out1 out2 out3 mc3 selin (carry in) selout (carry out) [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 38 of 85 7.2.2 datapath module the datapath contains an 8-bit si ngle cycle alu, with associated compare and condition generation logic. this datapath block is optimized to implement embedded functions, such as timers, counters, integrators, pwms, pr s, crc, shifters and dead band generators and many others. figure 7-8. datapath top level 7.2.2.6 working registers the datapath contains six primary working registers, which are accessed by cpu firmware or dma during normal operation. 7.2.2.7 dynamic datapath configuration ram dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. this is implemented using the 8-word x 16-bit configuration ram, which stores eight unique 16-bit wide configurations. the address input to this ram controls the sequence, and can be routed from any block connected to the udb routing matrix, most typically pld logic, i/o pins, or from the outputs of this or other datapath blocks. alu the alu performs eight general purpose functions. they are: ? increment ? decrement ? add ? subtract ? logical and ? logical or ? logical xor a0 a1 d0 d1 pi alu mask shift data registers output muxes f1 f0 fifos accumulators po a0 a1 d0 d1 output to programmable routing chaining control store ram 8 word x 16 bit parallel input/output (to/from programmable routing) input from programmable routing input muxes to/from next datapath to/from previous datapath datapath control phub system bus r/w access to all registers conditions: 2 compares, 2 zero detect, 2 ones detect overflow detect 6 6 table 7-1. working datapath registers name function description a0 and a1 accumulators these are sources and sinks for the alu and also sources for the compares. d0 and d1 data registers these are sources for the alu and sources for the compares. f0 and f1 fifos these are the primary interface to the system bus. they can be a data source for the data registers and accumulators or they can capture data from the accumu- lators or alu. each fifo is four bytes deep. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 39 of 85 independent of the alu operation, these functions are available: ? shift left ? shift right ? nibble swap ? bitwise or mask 7.2.2.8 conditionals each datapath has two compares, with bit masking options. compare operands include the two accumulators and the two data registers in a variety of configurations. other conditions include zero detect, all ones detect, and overflow. these condi- tions are the primary datapath outputs, a selection of which can be driven out to the udb routing matrix. conditional computation can use the built in chaining to neighboring udbs to operate on wider data widths without the need to use routing resources. 7.2.2.9 variable msb the most significant bit of an ar ithmetic and shift function can be programmatically specified. this supports variable width crc and prs functions, and in conjunction with alu output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.10 built in crc/prs the datapath has built in support for single cycle cyclic redun- dancy check (crc) computation and pseudo random sequence (prs) generation of arbitrary width and arbitrary polynomial. crc/prs functions longer than 8 bits may be imple- mented in conjunction with pld logic, or built in chaining may be use to extend the function into neighboring udbs. 7.2.2.11 input/output fifos each datapath contains two four-byte deep fifos, which can be independently configured as an input buffer (system bus writes to the fifo, datapath internal reads the fifo), or an output buffer (datapath internal writes to the fifo, the system bus reads from the fifo). the fifos genera te status that are selectable as datapath outputs and can ther efore be driven to the routing, to interact with sequencers, interrupts, or dma. figure 7-9. example fifo configurations 7.2.2.12 chaining the datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithmetic, shift, crc/prs functions. 7.2.2.13 time multiplexing in applications that are over sa mpled, or do not need high clock rates, the single alu block in the datapath can be efficiently shared with two sets of registers and condition generators. carry and shift out data from the alu are registered and can be selected as inputs in subsequent cycles. this provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.14 datapath i/o there are six inputs and six outputs that connect the datapath to the routing matrix. inputs from the routing provide the configu- ration for the datapath operation to perform in each cycle, and the serial data inputs. inputs can be routed from other udb blocks, other device peripherals, device i/o pins, and so on. the outputs to the routing can be s elected from the generated condi- tions, and the serial data outputs. outputs can be routed to other udb blocks, device peripherals, interrupt and dma controller, i/o pins, and so on. system bus f0 f1 system bus a0/a1/alu d0/d1 a0/a1/alu system bus f1 a0/a1/alu f0 d0 system bus f1 a0 d1 a1 f0 tx/rx dual capture dual buffer [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 40 of 85 7.2.3 status and control module the primary purpose of this circuitry is to coordinate cpu firmware interaction with internal udb operation. figure 7-10. status and control registers the bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of udb processing. the status register is read-only and it allows internal udb state to be read out onto the system bus directly from internal routing. this allows firmware to monitor the state of udb processing. each bit of these registers has programmable connections to the routing matrix and routing connections are made depending on the requirements of the application. 7.2.3.15 usage examples as an example of control input, a bit in the control register can be allocated as a function enable bit. there are multiple ways to enable a function. in one method the control bit output would be routed to the clock control block in one or more udbs and serve as a clock enable for the selected udb blocks. a status example is a case where a pld or datapath block generated a condition, such as a ?compare true? condition that is captured and latched by the status register and then read (and cleared) by cpu firmware. 7.2.3.16 clock generation each subcomponent block of a udb including the two plds, the datapath, and status and control, has a clock selection and control block. this promotes a fine granularity with respect to allocating clocking resources to udb component blocks and allows unused udb resources to be used by other functions for maximum system efficiency. 7.3 udb array description figure 7-11 shows an example of a 16 udb array. in addition to the array core, there are a dsi routing interfaces at the top and bottom of the array. other interfaces that are not explicitly shown include the system interfaces for bus and clock distribution. the udb array includes multiple horizontal and vertical routing channels each comprised of 96 wires. the wire connections to udbs, at horizontal/vertical intersection and at the dsi interface are highly permutable providing efficient automatic routing in psoc creator. additionally the routing allows wire by wire segmentation along the vertical an d horizontal routing to further increase routing flexibility and capability. figure 7-11. digital system interface structure 7.3.1 udb array programmable resources figure 7-12 shows an example of how functions are mapped into a bank of 16 udbs. the primary programmable resources of the udb are two plds, one datapath and one status/control register. these resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to other unrelated functions. an example of this is the 8-bit timer in the upper left corner of the array. this function only requires one datapath in the udb, and therefore the pld resources may be allocated to another function. a function such as a quadrature decoder may require more pld logic than one udb can supply and in this case can utilize the unused pld blocks in the 8-bit timer udb. program- mable resources in the udb array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. routing channel 8-bit status register (read only) 8-bit control register (write/read) system bus udb udb hv b udb udb hv a udb udb hv b hv a udb udb hv a udb udb hv b udb udb hv a hv b hv b hv a hv b hv a hv a hv b hv a hv b udb udb udb udb system connections system connections [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 41 of 85 figure 7-12. function mappin g example in a bank of udbs 7.4 dsi routing interface description the dsi routing interface is a continuation of the horizontal and vertical routing channels at the top and bottom of the udb array core. it provides general purpose programmable routing between device peripherals, including udbs, i/os, analog peripherals, interrupts, dma and fixed function peripherals. figure 7-13 illustrates the concept of the digital system inter- connect, which connects the udb array routing matrix with other device peripherals. any digital core or fixed function peripheral that needs programmable routing is connected to this interface. signals in this category include: ? interrupt requests from all di gital peripherals in the system. ? dma requests from all digi tal peripherals in the system. ? digital peripheral data signals that need flexible routing to i/os. ? digital peripheral data signals that need connections to udbs. ? connections to the interrupt and dma controllers. ? connection to i/o pins. ? connection to analog system digital signals. figure 7-13. digital system interconnect interrupt and dma routing is very flexible in the cy8c52 programmable architecture. in addition to the numerous fixed function peripherals that can generate interrupt requests, any data signal in the udb array routing can also be used to generate a request. a single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. figure 7-14 shows the structure of the idmux (interrupt/dma multiplexer). figure 7-14. interrupt and dma processing in the idmux udb udb hv b udb udb hv a udb udb hv b hv a udb hv a udb hv b udb hv a hv b udb udb udb udb udb udb uart logic 12-bit pwm i2c slave 8-bit spi 12-bit spi logic 8-bit timer 16-bit pyrs udb 8-bit timer quadrature decoder 16-bit pwm sequencer udb array digital system routing i/f digital system routing i/f can interrupt controller i2c io port pins dma controller global clocks comparators io port pins emif global clocks timer counters sar adc dma termout (irqs) dma controller interrupt controller fixed function irqs edge detect edge detect irqs udb array fixed function drqs drqs interrupt and dma processing in idmux 0 1 2 3 0 1 2 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 42 of 85 7.4.1 i/o port routing there are a total of 20 dsi routes to a typical 8-bit i/o port, 16 for data and four for drive strength control. when an i/o pin is connected to the routing, there are two primary connections available, an input and an output. in conjunction with drive strength control, this can implement a bidirectional i/o pin. a data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. the synchronization clock is the system clock (see figure 6-1 ). normally all inputs from pins are synchronized as this is required if the cpu interacts with the signal or any signal derived fr om it. asynchronous inputs have rare uses. an example of this is a feed through of combinational pld logic from input pins to output pins. figure 7-15. i/o pin synchronization routing figure 7-16. i/o pin output connectivity there are four more dsi connections to a given i/o port to implement dynamic output enable co ntrol of pins. this connec- tivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. the output enable signal is useful for creating tri-state bidirectional pins and buses. figure 7-17. i/o pin output enable connectivity 7.5 can the can peripheral is a fully functional controller area network (can) supporting communication baud rates up to 1 mbps. the can controller implements the can2.0a and can2.0b specifi- cations as defined in the bosch specification and conforms to the iso-11898-1 standard. the can protocol was originally designed for automotive applications with a focus on a high level of fault detection. this ensures high communication reliability at a low cost. because of its succe ss in automotive applications, can is used as a standard communication protocol for motion oriented machine control networks (canopen) and factory automation applications (devicenet). the can controller features allow the efficient implementation of higher level protocols without affecting t he performance of the microcon- troller cpu. full configuration support is provided in psoc creator. do di port i pin 0 do pin1 do pin2 do pin3 do pin4 do pin5 do pin6 do pin7 do 8 io data output connections from the udb array digital system interface port i pin 0 oe pin1 oe pin2 oe pin3 oe pin4 oe pin5 oe pin6 oe pin7 oe 4 io control signal connections from udb array digital system interface [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 43 of 85 figure 7-18. can bus system implementation 7.5.1 can features ? can2.0a/b protocol implementation - iso 11898 compliant ? standard and extended frames with up to 8 bytes of data per frame ? message filter capabilities ? remote transmission request (rtr) support ? programmable bit rate up to 1 mbps ? listen only mode ? sw readable error counter and indicator ? sleep mode: wake the device from sleep with activity on the rx pin ? supports two or three wire interface to external transceiver (tx, rx, and enable). the three-wire interface is compatible with the philips phy; the phy is not included on-chip. the three wires can be routed to any i/o ? enhanced interrupt controller ? can receive and transmit buffers status ? can controller error status including busoff ? receive path ? 16 receive buffers each with its own message filter ? enhanced hardware message filter implementation that cov- ers the id, ide and rtr ? devicenet addressing support ? multiple receive buffers linkable to build a larger receive mes- sage array ? automatic transmission request (rtr) response handler ? lost received message notification ? transmit path ? eight transmit buffers ? programmable transmit priority ? round robin ? fixed priority ? message transmissions abort capability 7.5.2 software tools support can controller configuration integrated into psoc creator: ? can configuration walkthrough with bit timing analyzer ? receive filter setup can node 1 psoc can controller can transceiver tx rx en can node 2 can node n can_h can_l can_h can_l can_h can_l can drivers can bus [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 44 of 85 figure 7-19. can controller block diagram 7.6 usb psoc includes a dedicated full-speed (12 mbps) usb 2.0 trans- ceiver supporting all four usb transfer types: control, interrupt, bulk, and isochronous. the maximum data payload size is 64 bytes for control, interrupt, and bulk endpoints and 1023 bytes for isochronous. psoc creator provides full configuration support. usb interfaces to hosts through two dedicated usbio pins, which are detailed in the ?i/o system and routing? section on page 26. usb includes the following features: ? eight unidirectional data endpoints ? one bidirectional control endpoint 0 (ep0) ? shared 512-byte buffer for the eight data endpoints ? dedicated 8-byte buffer for ep0 ? three memory modes ? manual memory management with no dma access ? manual memory management with manual dma access ? automatic memory management with automatic dma ac- cess ? internal 3.3v regulator for transceiver ? internal 48 mhz oscillator that auto locks to usb bus clock, requiring no external crystal for usb (usb equipped parts only) ? interrupts on bus and each endpoint event, with device wakeup ? usb reset, suspend, and resume operations ? bus powered and self powered modes figure 7-20. usb txmessage0 txreq txabort txmessage7 txreq txabort txmessage1 txreq txabort txmessage6 txreq txabort priority arbiter rxmessage0 rxmessage15 rxmessage1 rxmessage14 rxmessage handler acceptance code 0 acceptance mask 0 acceptance code 1 acceptance mask 1 acceptance code 14 acceptance mask 14 acceptance code 15 acceptance mask 15 rtr rxmessages 0-15 tx can framer crc generator rx can framer crc check bit timing error detection crc form ack bit stuffing bit error overload arbitration txinterrupt request (if enabled) rxinterrupt request (if enabled) error status error active error passive bus off tx error counter rx error counter errinterrupt request (if enabled) wakeup request rx buffer status rxmessage available tx buffer status txreq pending rx tx s i e (serial interface engine) 48 mhz imo arbiter 512 x 8 sram usb io d+ d- interrupts system bus [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 45 of 85 7.7 timers, counters, and pwms the timer/counter/pwm peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features . as almost all embedded systems use some combination of timers, counters, and pwms. four of them have been included on this psoc device family. additional and more advanced functionality timers, counters, and pwms can also be instantiated in universal digi tal blocks (udbs) as required. psoc creator allows designers to choose the timer, counter, and pwm features that they require. the tool set utilizes the most optimal resources available. the timer/counter/pwm peripheral can select from multiple clock sources, with input and output signals connected through the dsi routing. dsi routing allo ws input and output connections to any device pin and any internal digital signal accessible through the dsi. each of the four instances has a compare output, terminal count output (optional complementary compare output), and programmable interrupt request line. the timer/counter/pwms are configurable as free running, one shot, or enable input controlled. the peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. the peripheral supports full 16-bit capture. timer/counter/pwm features include: ? 16-bit timer/counter/pwm (down count only) ? selectable clock source ? pwm comparator (configurable for lt, lte, eq, gte, gt) ? period reload on start, reset, and terminal count ? interrupt on terminal count, compare true, or capture ? dynamic counter reads ? timer capture mode ? count while enable signal is asserted mode ? free run mode ? one shot mode (stop at end of period) ? complementary pwm outputs with deadband ? pwm output kill figure 7-21. timer/counter/pwm 7.8 i 2 c the i 2 c peripheral provides a synchronous two wire interface designed to interface the psoc device with a two wire i 2 c serial communication bus. the bus is compliant with philips ?the i 2 c specification? version 2.1. additional i 2 c interfaces can be instantiated using universal di gital blocks (udbs) in psoc creator, as required. to eliminate the need for excessive cpu intervention and overhead, i 2 c specific support is provided for status detection and generation of framing bits. i 2 c operates as a slave, a master, or multimaster (slave and mast er). in slave mode, the unit always listens for a start condition to begin sending or receiving data. master mode supplies the ability to generate the start and stop conditions and initiate transactions. multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. if master mode is enabled and slave mode is not enabled, the block does not generate interrupts on externally generated start conditions. i 2 c interfaces through the dsi routing and allows direct connections to any gpio or sio pins. i 2 c provides hardware address detect of a 7-bit address without cpu intervention. additionally the device can wake from low power modes on a 7-bit hardware address match. if wakeup functionality is required, i 2 c pin connections are limited to the two special sets of sio pins. i 2 c features include: ? slave and master, transmitter, and receiver operation ? byte processing for low cpu overhead ? interrupt or polling cpu interface ? support for bus speeds up to 1 mbps (3.4 mbps in udbs) ? 7 or 10-bit addressing (10-bit addressing requires firmware support) ? smbus operation (through firmware support - smbus supported in hardware in udbs) ? 7-bit hardware address compare ? wake from low power modes on address match 8. analog subsystem the analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. these blo cks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and ip security. the features of the analog subsystem are outlined here to provide an overview of capabilities and architecture. ? flexible, configurable analog r outing architecture provided by analog globals, analog mux bus, and analog local buses ? successive approximation (sar) adc ? two comparators with optional connection to configurable lut outputs ? capsense subsystem to enabl e capacitive touch sensing ? precision reference for generating an accurate analog voltage for internal analog blocks timer / counter / pwm 16-bit clock reset enable capture kill irq compare tc / compare! [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 46 of 85 figure 8-1. analog subsystem block diagram the psoc creator software program provides a user friendly interface to configure the analog connections between the gpio and various analog resources and also connections from one analog resource to another. psoc creator also provides component libraries that allow you to configure the various analog blocks to perform applicat ion specific functions. the tool also generates api interface libra ries that allow you to write firmware that allows the communication between the analog peripheral and cpu/memory. 8.1 analog routing the cy8c38 family of devices has a flexible analog routing architecture that provides the capability to connect gpios and different analog blocks, and also route signals between different analog blocks. one of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the di fferent analog blocks. 8.1.1 features ? flexible, configurable analog routing architecture ? 16 analog globals (ag) and two analog mux buses (amuxbus) to connect gpios and the analog blocks ? each gpio is connected to one analog global and one analog mux bus ? 8 analog local buses (abus) to route signals between the different analog blocks ? multiplexers and switches for in put and output selection of the analog blocks 8.1.2 functional description analog globals (ags) and analog mux buses (amuxbus) provide analog connectivity between gpios and the various analog blocks. there are 16 ags in the cy8c38 family. the analog routing architecture is divided into four quadrants as shown in figure 8-2 . each quadrant has four analog globals (agl[0..3], agl[4..7], agr[0..3 ], agr[4..7]). each gpio is connected to the corresponding ag through an analog switch. the analog mux bus is a shared routing resource that connects to every gpio through an analog switch. there are two amuxbus routes in cy8c38, one in the left half (amuxbusl) and one in the right half (amuxbusr), as shown in figure 8-2 . analog interface precision reference cmp cmp capsense subsystem dsi array clock distribution config & status registers phub cpu comparators ahb gpio port gpio port sar a n a l o g r o u t i n g a n a l o g r o u t i n g [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 47 of 85 figure 8-2. cy8c52 analog interconnect vio0 sio p12[3] sio p12[2] gpio p15[3] gpio p15[2] sio p12[1] sio p12[0] gpio p3[7] gpio p3[6] vio3 vccd vssd vssio vddd gpio p6[0] gpio p6[3] gpio p6[2] gpio p6[1] gpio p15[4] gpio p15[5] gpio p2[0] gpio p2[4] gpio p2[3] gpio p2[2] gpio p2[1] vio2 gpio p2[5] gpio p2[7] gpio p2[6] sio p12[4] sio p12[5] gpio p6[4] gpio p6[5] gpio p6[6] gpio p6[7] vio1 sio p12[6] sio p12[7] usb io p15[6] usb io p15[7] vusb vddd vssd vssio vccd gpxt p15[0] gpxt p15[1] gpio p3[5] gpio p3[4] gpio p3[3] gpio p3[2] gpio p3[1] agr[4] agr[7] agr[6] agr[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] *** * * * * * * * * * denotes pins on all packages 76543210 76543210 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 comp0 comp1 comparator + - + - agl[4] agl[7] agl[6] agl[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] agr[4] agr[7] agr[6] agr[5] notes: amuxbusr amuxbusl i1 i3 i2 i0 rev #43 22-apr-2009 vssa vsab vssd vcca gpio p0[5] * gpio p0[7] * gpio p1[3] gpio p1[2] gpio p1[1] gpio p1[0] * * * * gpio p1[4] * gpio p1[5] * gpio p1[6] * gpio p1[7] * gpio p5[7] gpio p5[6] gpio p5[5] gpio p5[4] gpio p4[4] gpio p4[7] gpio p4[6] gpio p4[5] gpio p5[2] gpio p5[3] gpio p5[1] gpio p5[0] gpio p4[3] gpio p4[2] abusl0 vssio vdab * * ** * * * * * * * * * * * agl[4] agl[7] agl[6] agl[5] gpio p4[0] gpio p4[1] vssa amuxbusl amuxbusr amuxbusl amuxbusr amuxbusl amuxbusr abusl1 abusl2 abusl3 abusr3 abusr2 abusr1 abusr0 exvrefl exvrefr ind vssb vb vssio xres_n vssd * * * * vbat 90 13 44 gpio p3[0] gpio p0[6] * lpf in0 out0 in1 out1 5 mux group switch group connection large (lower z) small (higher z) # 266 93/122 size other: dft 24 small lcd 15 small vss ref aux adc gpio p0[0] * gpio p0[1] * gpio p0[2] * gpio p0[3] * gpio p0[4] * vpwra, vpwra/2 vda, vda/4 amuxbusr amuxbusl analog globals analog bus 0123 3210 analog bus analog globals refbufr refbufl in out ref in out ref vssa capsense vssa sar adc sar0 vp (+) vn (-) exvrefl2 exvrefl1 refs vrefhi_out vda, vda/2 vda, vda/2 exvrefl1 exvrefl2 1.024v 1.024v 0.256v vda, vda/2 1.024v 1.024v 1.024v 1.2v 1.024v 1.2v 0.8v 0.7v 1.2v 1.024v 1.2v 1.024v 1.2v 1.024v 1.024v 1.024v 3210 0123 cy8c55 only lcd signals are not shown. * : vdda * lpf vbe [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 48 of 85 analog local buses (abus) are routing resources located within the analog subsystem and are used to route signals between different analog blocks. there are eight abus routes in cy8c38, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in figure 8-2 . using the abus saves the analog globals and analog mux buses from being used for intercon- necting the analog blocks. multiplexers and switches exist on the various buses to direct signals into and out of the anal og blocks. a multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. in figure 8-2 , multi- plexers are indicated by grayed ovals and switches are indicated by transparent ovals. 8.2 successive approximation adc the cy8c52 family of devices has a successive approximation (sar) adc. this adc is 12-bit at up to 1 msps, with single-ended or differential inputs, making it useful for a wide variety of sampling and control applications. 8.2.1 functional description in a sar adc an analog input signal is sampled and compared with the output of a dac. a bina ry search algorithm is applied to the dac and used to determine the output bits in succession from msb to lsb. a block diagram of the sar adc is shown in figure 8-3 . figure 8-3. sar adc block diagram the input is connected to the analog globals and muxes. the frequency of the clock is 16 time s the sample rate; the maximum clock rate is 16 mhz. 8.2.2 conversion signals writing a start bit or assertion of a start of frame (sof) signal is used to start a conversion. sof can be used in applications where the sampling period is longer than the conversion time, or when the adc needs to be synchronized to other hardware. this signal is optional and does not need to be connected if the sar adc is running in a continuous mode. a digital clock or udb output can be used to drive this input. when the sar is first powered up or awakened from any of the sleeping modes, there is a power up wait time of 10 s before it is ready to start the first conversion. when the conversion is complete, a status bit is set and the output signal end of frame (eof) asserts and remains asserted until the value is read by either the dma controller or the cpu. the eof signal may be used to trigger an interrupt or a dma request. 8.2.3 operational modes a one_shot control bit is used to set the sar adc conversion mode to either continuous or one conversion per sof signal. dma transfer of continuous samples, without cpu intervention, is supported. 8.3 comparators the cy8c52 family of devices contains two comparators in a device. comparators have these features: ? input offset factory trimmed to less than 5 mv ? rail-to-rail common mode input range (vssa to vcca) ? speed and power can be traded off by using one of three modes: fast, slow, or ultra low power ? comparator outputs can be routed to look up tables to perform simple logic functions and then can also be routed to digital blocks ? the positive input of the comparators may be optionally passed through a low pass filter. two filters are provided ? comparator inputs can be connected to gpio 8.3.1 input and output interface the positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. the output from each comparator could be routed to any of the two input luts. the output of that lut is routed to the udb digital system interface. s/ h dac array vin vrefp vrefn comparator sar digital d0:d11 clock autozero reset clock d0:d11 power filtering power ground vrefp vrefn [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 49 of 85 figure 8-4. analog comparator 8.3.2 lut the cy8c52 family of devices contains two luts. the lut is a two input, one output lookup table t hat is driven by one or two of the comparators in the chip. the output of any lut is routed to the digital system interface of the udb array. from the digital system interface of the udb array, these signals can be connected to udbs, dma controller, i/o, or the interrupt controller. the lut control word written to a register sets the logic function on the output. the available lut functions and the associated control word is shown in ta b l e 8 - 1 . 8.4 lcd direct drive the psoc liquid crystal display (lcd) driver system is a highly configurable peripheral designed to allow psoc to directly drive a broad range of lcd glass. all voltages are generated on chip, eliminating the need for external components. with a high multiplex ratio of up to 1/16, the cy8c52 family lcd driver system can drive a maximum of 736 segments. the psoc lcd driver module was also designed with the conservative power budget of portable devices in mind, enabling different lcd drive modes and power down modes to conserve power. psoc creator provides an lcd segment drive component. the component wizard provides easy and flexible configuration of lcd resources. you can specify pins for segments and anaif + _ + _ comp0 comp1 4 lut0 lut1 lut2 lut3 4 4 4 4 4 4 4 from analog routing from analog routing udbs table 8-1. lut function vs. program word and inputs control word output (a and b are lut inputs) 0000b false (?0?) 0001b a and b 0010b a and (not b ) 0011b a 0100b (not a ) and b 0101b b 0110b a xor b 0111b a or b 1000b a nor b 1001b a xnor b 1010b not b 1011b a or (not b ) 1100b not a 1101b (not a ) or b 1110b a nand b 1111b true (?1?) table 8-1. lut function vs. program word and inputs (con- control word output (a and b are lut inputs) [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 50 of 85 commons along with other options. the software configures the device to meet the required s pecifications. th is is possible because of the programmability inherent to psoc devices. key features of the psoc lcd segment system are: ? lcd panel direct driving ? type a (standard) and type b (low power) waveform support ? wide operating voltage range support (2v to 5v) for lcd panels ? static, 1/2, 1/3, 1/4, 1/5 bias voltage levels ? internal bias voltage generation through internal resistor ladder ? up to 62 total common and segment outputs ? up to 1/16 multiplex for a maximum of 16 backplane/common outputs ? up to 62 front plane/segment outputs for direct drive ? drives up to 736 total segments (16 backplane x 46 front plane) ? up to 128 levels of software controlled contrast ? ability to move display data from memory buffer to lcd driver through dma (without cpu intervention) ? adjustable lcd refresh rate from 10 hz to 150 hz ? ability to invert lcd display for negative image ? three lcd driver drive modes, allowing power optimization ? lcd driver configurable to be active when psoc is in limited active mode figure 8-5. lcd system 8.4.1 lcd segment pin driver each gpio pin contains an lcd driver circuit. the lcd driver buffers the appropriate output of the lcd dac to directly drive the glass of the lcd. a register setting determines whether the pin is a common or segment. the pin?s lcd driver then selects one of the six bias voltages to drive the i/o pin, as appropriate for the display data. 8.4.2 display data flow the lcd segment driver system reads display data and generates the proper output voltages to the lcd glass to produce the desired image. display data resides in a memory buffer in the system sram. each time you need to change the common and segment driver volt ages, the next set of pixel data moves from the memory buffer into the port data registers via dma. 8.4.3 udb and lcd segment control a udb is configured to generate the global lcd control signals and clocking. this set of signals is routed to each lcd pin driver through a set of dedicated lcd global routing channels. in addition to generating the global lcd control signals, the udb also produces a dma request to initiate the transfer of the next frame of lcd data. 8.4.4 lcd dac the lcd dac generates the cont rast control and bias voltage for the lcd system. the lcd dac produces up to five lcd drive voltages plus ground, based on the selected bias ratio. the bias voltages are driven out to gpio pins on a dedicated lcd bias bus, as required. 8.5 capsense the capsense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity de tection, etc. the capsense system uses a configuration of system resources, including a few hardware functions primarily targeted for capsense, to realize various sensing algorithms. specific resource usage is detailed in the capsense component in psoc creator. a capacitive sensing method using a delta-sigma modulator (csd) is used. it provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. 8.6 temp sensor die temperature is used to establish programming parameters for writing flash. die temperature is measured using a dedicated sensor based on a forward biased transistor. the temperature sensor has its own auxiliary adc. lcd driver block udb dma display ram lcd dac pin global clock phub [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 51 of 85 9. programming, debug interfaces, resources the cortex-m3 has internal debugging components, tightly integrated with the cpu, prov iding the following features: ? jtag or swd access ? flash patch and breakpoint (fpb) block for implementing breakpoints and code patches ? data watchpoint and trigger (dwt) block for implementing watchpoints, trigger resour ces, and system profiling ? embedded trace macrocell (etm) for instruction trace ? instrumentation trace macrocell (itm) for support of printf-style debugging psoc devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. four interfaces are available: jtag, swd, swv, and traceport. jtag and swd support all programming and debug features of the device. jtag also supports standard jtag scan chains for board level test and chaining multiple jtag devices for programming or testing. the swv and traceport provide trace output from the dwt, etm, and itm. traceport is faster but uses more pins. swv is slower but uses only one pin. cortex-m3 debug and trace functionality enables full device debugging in the final system using the standard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator ide software provides fully integrated programming and debug support for psoc devices. the low cost miniprog3 programmer and debugger is designed to provide full programming and debug support of psoc devices in conjunction with the psoc creator ide. pso c jtag, swd, and swv inter- faces are fully compatible with industry standard third party tools. all cortex-m3 debug and trace modules are disabled by default and can only be enabled in firmware. if not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables them. disabling debug and trace features, robust flash protection, and hiding custom analog and digital functionality inside the psoc device provide a level of security not possible with multichip application solutions. additionally, all device inter- faces can be permanently disabled (device security) for applica- tions concerned about phishing attacks due to a maliciously reprogrammed device. permanently disabling interfaces is not recommended in most applicat ions because the designer then cannot access the device. because all programming, debug, and test interfaces are disabled when device security is enabled, psocs with device security enabled may not be returned for failure analysis. 9.1 jtag interface the ieee 1149.1 compliant jtag interface exists on four or five pins (the ntrst pin is optional). the jtag clock frequency can be up to 8 mhz. by default, the jtag pins are enabled on new devices but the jtag interface can be disabled, allowing these pins to be used as general pu rpose i/o (gpio) instead. the jtag interface is used for programming the flash memory, debugging, i/o scan chains, and jtag device chaining. 9.2 swd interface the swd interface is the pref erred alternative to the jtag interface. it requires only two pins instead of the four or five needed by jtag. swd provides all of the programming and debugging features of jtag at the same speed. swd does not provide access to scan chains or device chaining. swd uses two pins, either two of the jtag pins (tms and tck) or the usbio d+ and d- pins. th e usbio pins are useful for in system programming of usb solutions that would otherwise require a separate programming connector. one pin is used for the data clock and the other is used for data input and output. swd can be enabled on only one of the pin pairs at a time. this only happens if, within 8 s (key window) after reset, that pin pair (jtag or usb) receives a predetermined sequence of 1s and 0s. swd is used for debugging or for programming the flash memory. the swd interface can be enabl ed from the jtag interface or disabled, allowing its pins to be used as gpio. unlike jtag, the swd interface can always be reacquired on any device during the key window. it can then be used to reenable the jtag interface, if desired. when using swd or jtag pins as standard gpio, make sure that the gpio functionality and pcb circuits do not interfere with swd or jtag use. 9.3 debug features the cy8c52 supports the following debug features: ? halt and single-step the cpu ? view and change cpu and peripheral registers, and ram addresses ? six program address breakpoints and two literal access break- points ? data watchpoint events to cpu ? patch and remap instruction from flash to sram ? debugging at the full speed of the cpu ? debug operations are possible while the device is reset, or in low power modes ? compatible with psoc creator and miniprog3 programmer and debugger ? standard jtag programming and debugging interfaces make cy8c52 compatible with other popular third-party tools (for example, arm / keil) [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 52 of 85 9.4 trace features the following trace features are supported: ? instruction trace ? data watchpoint on access to data address, address range, or data value ? trace trigger on data watchpoint ? debug exception trigger ? code profiling ? counters for measuring clock cycles, folded instructions, load/store operations, sleep cycles, cycles per instruction, interrupt overhead ? interrupt events trace ? software event monitoring, ?printf-style? debugging 9.5 swv and traceport interfaces the swv and traceport interfaces provide trace data to a debug host via the cypress miniprog3 or an external trace port analyzer. the 5 pin traceport is used for rapid transmission of large trace streams. the single pin swv mode is used to minimize the number of trace pins. swv is shared with a jtag pin. if debugging and tracing are done at the same time then swd may be used with either swv or traceport, or jtag may be used with traceport, as shown in table 9-1 . 9.6 programming features the jtag and swd interfaces provide full programming support. the entire device can be erased, programmed, and verified. designers can increas e flash protection levels to protect firmware ip. flash protection can only be reset after a full device erase. individual flash blocks can be erased, programmed, and verified, if bloc k security settings permit. 9.7 device security psoc 5 offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. the device security is activated by programming a 32-bit key (0x50536f43) to a write once latch (wol). the write once latch is a type of nonvolatile latch (nvl). the cell itself is an nvl with additional logic wrapped around it. each wol device contains four bytes (32 bits) of data. the wrapper outputs a ?1? if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536f 43); it outputs a ?0? if this majority is not reached. when th e output is 1, the write once nv latch locks the part out of debug and test modes; it also perma- nently gates off the ability to erase or alter the contents of the latch. matching all bits is intent ionally not required, so that single (or few) bit failures do not deassert the wol output. the state of the nvl bits after wafer processing is truly random with no tendency toward 1 or 0. the wol only locks the part af ter the correct 32-bit key (0x50536f43) is loaded into the nvl's volatile memory, programmed into the nvl's nonvolatile cells, and the part is reset. the output of the wol is only sampled on reset and used to disable the access. this precaution prevents anyone from reading, erasing, or altering the contents of the internal memory. the user can write the key into the wol to lock out external access only if no flash protection is set (see ?flash security? section on page 15). however, after setting the values in the wol, a user still has access to the part until it is reset. therefore, a user can write the key into the wol, program the flash protection data, and then reset the part to lock it. if the device is protected with a wol setting, cypress cannot perform failure analysis and, t herefore, cannot accept rmas from customers. the wol can be read out via serial wire debug (swd) port to electrically identif y protected parts. the user can write the key in wol to lock out external access only if no flash protection is set. for more information on how to take full advantage of the security features in psoc see the psoc 5 trm. disclaimer note the following details of the flash code protection features on cypress devices. cypress products meet the spec ifications contained in their particular cypress data sheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. any of th ese methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaran- teeing the product as ?unbreakable.? cypress is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress are committed to continuously improving the code protection features of our products. table 9-1. debug configurations debug and trace configuration gpio pins used all debug and trace disabled 0 jtag 4 or 5 swd 2 swv 1 traceport 5 jtag + traceport 9 or 10 swd + swv 3 swd + traceport 7 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 53 of 85 10. development support the cy8c52 family has a rich set of documentation, devel- opment tools, and online resources to assist you during your development process. visit psoc.cypress.com/getting-started to find out more. 10.1 documentation a suite of documentation, to ensu re that you can find answers to your questions quickly, supports the cy8c52 family. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in de tail, how to use source control with psoc creator, and much more. component data sheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component data sheets provide all of the information needed to select and use a particular component, including a functional description, api documentation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include brushless dc motor control and on-chip filtering. application notes often include example projects in addition to the application note document. technical reference manual : psoc creator makes designing with psoc as easy as dragging a peripheral onto a schematic, but, when low level details of the psoc device are required, use the technical reference manual (trm) as your guide. note visit www.arm.com for detailed documentation about the cortex-m3 cpu. 10.2 online in addition to print documentation, the cypress psoc forums connect you with fellow psoc users and experts in psoc from around the world, 24 hours a day, 7 days a week. 10.3 tools with industry standard cores, programming, and debugging interfaces, the cy8c52 family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use cydesign ide, supported third party compilers, programmers, debuggers, and development kits. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 54 of 85 11. electrical specifications specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. the unique flexibil ity of the psoc udbs and analog blocks enable many functions to be implemented in psoc creator components, see the component data sheets for full ac/dc specifications of individual functions. see the ?example peripherals? section on page 33 for further expl anation of psoc creator components. 11.1 absolute maximum ratings note usage above the absolute maximum conditions listed in ta b l e 11 - 1 may cause permanent damage to the device. exposure to maximum conditions for extended periods of time may affect device reliability. when used below maximum conditions but above normal operating conditions the devic e may not operate to specification. table 11-1. absolute maximu m ratings dc specifications parameter description conditions min typ max units tstorag storage temperature recommended storage temper- ature is 0c - 50c. exposure to storage temperatures above 85c for extended periods may affect device reliability. -55 25 125 c vdda analog supply voltage relative to vssa -0.5 - 6 v vddd digital supply voltage relative to vssd -0.5 - 6 v vddio i/o supply voltage relative to vssd -0.5 - 6 v vcca direct analog core voltage input -0.5 - 1.95 v vccd direct digital core voltage input -0.5 - 1.95 v vssa analog ground voltage vssd -0.5 - vssd + 0.5 v vgpio [6] dc input voltage on gpio includes signals sourced by vdda and routed internal to the pin. vssd -0.5 - vddio + 0.5 v vsio dc input voltage on sio output disabled vssd -0.5 - 7 v output enabled vssd -0.5 - 6 v vind voltage at boost converter input 0.5 - 5.5 v vbat boost converter supply vssd -0.5 - 5.5 v ivddio current per vddio supply pin - - 100 ma lu latch up current -200 - 200 ma esd hbm electro-static discharge voltage human body model 2000 - - v esd cdm electro-static discharge voltage charge device model 500 - - v note 6. the vddio supply voltage must be greater than the maximum anal og voltage on the associated gpio pins. maximum analog voltage on gpio pin vddio vdda. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 55 of 85 11.2 device level specifications specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.2.1 device level specifications table 11-2. dc specifications parameter description conditions min typ max units vdda analog supply voltage and input to analog core regulator analog core regulator enabled 1.8 5.5 v vdda analog supply voltage, analog regulator bypassed analog core regulator disabled 1.71 1.8 1.89 v vddd digital supply voltage relative to vssd digital core regulator enabled 1.8 vdda v vddd digital supply voltage, digital regulator bypassed digital core regulator disabled 1.71 1.8 1.89 v vddio [6] i/o supply voltage relative to vssio 1.71 vdda v vcca direct analog core voltage input (analog regulator bypass) analog core regulator disabled 1.71 1.8 1.89 v vccd direct digital core voltage input (digital regulator bypass) digital core regulator disabled 1.71 1.8 1.89 v vbat voltage supplied to boost converter 0.5 5.5 v active mode, vdd = 1.71v - 5.5v idd [8] execute from flash, cpu at 6 mhz t= -40c ma t= 25c 2 ma t= 85c ma sleep mode [7] cpu off rtc = on (= eco32k on, in low power mode) wdt = off i 2 c wake = off comparator = off por = on boost = off sio pins in single ended input, unregulated output mode vdd = vddio = 4.5 - 5.5v t= -40c a t= 25c a t= 85c a vdd = vddio = 2.7 - 3.6v t= -40c a t= 25c 2 a t= 85c a vdd = vddio = 1.71 - 1.95v t= -40c a t= 25c a t= 85c a hibernate mode [7] hibernate mode current all regulators and oscillators off. sram retention gpio interrupts are active boost = off sio pins in single ended input, unregulated output mode vdd = vddio = 4.5 - 5.5v t= -40c na t= 25c na t= 85c na vdd = vddio = 2.7 - 3.6v t= -40c na t= 25c 300 na t= 85c na vdd = vddio = 1.71 - 1.95v t= -40c na t= 25c na t= 85c na note 7. if vccd and vcca are externally regulated, the voltage di fference between vccd and vcca must be less than 50 mv. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 56 of 85 notes 8. the current consumption of additional peripherals that are im plemented only in programmed logic blocks can be found in their respective data sheets, available in psoc creator, the integrated design environment. to compute total current, find cpu current at frequency of interest and add pe ripheral currents for your particular system from the device data sheet and component data sheets. 9. based on device characterization (not production tested). table 11-3. ac specifications [9] parameter description conditions min typ max units f cpu cpu frequency 1.71v vddd 5.5v dc - 40 mhz f busclk bus frequency 1.71v vddd 5.5v dc - 40 mhz svdd vdd ramp rate 1.00e-04 - 1.00e+06 v/ms tio_init time from vddd/vdda/vccd/vcca ipor to i/o ports set to their reset states --10s ts ta r t u p time from vddd/vdda/vccd/vcca ppor to cpu executing code at reset vector vcca/vdda = regulated from vdda/vddd, no pll used, fast boot mode --9s vcca/vccd = regulated from vdda/vddd, no pll used, slow boot mode --36s tsleep wakeup from limited active mode - application of external interrupt to beginning of execution of next cpu instruction --12s thibernate wakeup form hibernate mode - application of external interrupt to beginning of execution of next cpu instruction --100s external reset pulse width 1 - - s [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 57 of 85 11.3 power regulators specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.3.1 digital core regulator 11.3.2 analog core regulator 11.3.3 inductive boost regulator table 11-4. digital core regulator dc specifications parameter description conditions min typ max units vddd input voltage 1.8 - 5.5 v vccd output voltage - 1.80 - v regulator output capacitance total capacitance on the two vccd pins. each capacitor is 10%, x5r ceramic or better, see power system on page 22 -1.1-f table 11-5. analog core regulator dc specifications parameter description conditions min typ max units vdda input voltage 1.8 - 5.5 v vcca output voltage - 1.80 - v regulator output capacitor 10%, x5r ceramic or better - 1 - f table 11-6. inductive boost regulator dc specifications parameter description conditions min typ max units vbat input voltage includes startup 0.5 - 5.5 v iboost load current [10, 11] vin=1.6-5.5v, vout=1.6-5.0v, external diode --50ma vin=1.6-3.6v, vout=1.6-3.6v, internal diode - - 75 ma vin=0.8-1.6v, vout=1.6-3.6v, internal diode - - 30 ma vin=0.8-1.6v, vout=3.6-5.0v, external diode --20ma vin=0.5-0.8v, vout=1.6-3.6v, internal diode - - 15 ma lboost boost inductor 10 h spec'd 4.7 10 47 h cboost filter capacitor [9] 22 f || 0.1 f spec'd 10 22 47 f if external schottky diode average forward current external schottky diode is required for vboost > 3.6v 1--a vr external schottky diode peak reverse voltage external schottky diode is required for vboost > 3.6v 20 - - v ilpk inductor peak current - - 700 ma quiescent current boost active mode - 200 - a boost standby mode, 32 khz external crystal oscillator, iboost < 1 a -12-a notes 10. for output voltages above 3.6v, an external diode is required. 11. maximum output current applies for output voltages 4x input voltage. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 58 of 85 vboost boost output voltage range [9] 1.8v 1.71 1.80 1.89 v 1.9v 1.81 1.90 2.00 v 2.0v 1.90 2.00 2.10 v 2.4v 2.28 2.40 2.52 v 2.7v 2.57 2.70 2.84 v 3.0v 2.85 3.00 3.15 v 3.3v 3.14 3.30 3.47 v 3.6v 3.42 3.60 3.8 v 5.0v external diode r equired 4.75 5.00 5.25 v efficiency vbat = 2.4 v, vout = 2.7 v, iout = 10 ma, fsw = 400 khz 90 - - % table 11-6. inductive boost regulator dc specifications (continued) parameter description conditions min typ max units table 11-7. inductive boost regulator ac specifications parameter description conditions min typ max units vripple ripple voltage (peak-to-peak) vout = 1.8v, fsw = 400 khz, iout = 10 ma - - 100 mv fsw switching frequency - 0.1, 0.4, or 2 -mhz duty cycle 20 - 80 % [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 59 of 85 11.4 inputs and outputs specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.4.1 gpio table 11-8. gpio dc specifications parameter description conditions min typ max units vih input voltage high threshold cmos input, prt[x]ctl = 0 0.7 vddio - - v vil input voltage low threshold cmos input, prt[x]ctl = 0 - - 0.3 vddio v vih input voltage high threshold lvttl input, prt[x]ctl = 1,vddio < 2.7v 0.7 x vddio - - v vih input voltage high threshold lvttl input, prt[x]ctl = 1, vddio 2.7 v 2.0 - - v vil input voltage low threshold lvttl input, prt[x]ctl = 1,vddio < 2.7v - - 0.3 x vddio v vil input voltage low threshold lvttl input, prt[x]ctl = 1, vddio 2.7 v --0.8v voh output voltage high ioh = 4 ma at 3.3 vddio vddio - 0.6 - - v ioh = 1 ma at 1.8 vddio vddio - 0.5 - - v vol output voltage low iol = 8 ma at 3.3 vddio - - 0.6 v iol = 4 ma at 1.8 vddio - - 0.6 v rpullup pull up resistor 4 5.6 8 k rpulldown pull down resistor 4 5.6 8 k iil input leakage current (absolute value) [9] 25c, vddio = 3.0v - - 2 na cin input capacitance [9] --7pf vh input voltage hysteresis (schmitt-trigger) [9] -40-mv idiode current through protection diode to vddio and vssio - - 100 a rglobal resistance pin to analog global bus 25c, vddio = 3.0v - 240 - rmux resistance pin to analog mux bus 25c, vddio = 3.0v - 130 - table 11-9. gpio ac specifications parameter description conditions min typ max units trisef rise time in fast strong mode [9] 3.3v vddio cload = 25 pf 2 - 12 ns tfallf fall time in fast strong mode [9] 3.3v vddio cload = 25 pf 2 - 12 ns trises rise time in slow strong mode [9] 3.3v vddio cload = 25 pf 10 - 60 ns tfalls fall time in slow strong mode [9] 3.3v vddio cload = 25 pf 10 - 60 ns fgpioout gpio output operating frequency 3.3v < vddio < 5.5v, fast strong drive mode 90/10% vddio into 25 pf - - 33 mhz 1.71v < vddio < 3.3v, fast strong drive mode 90/10% vddio into 25 pf - - 20 mhz 3.3v < vddio < 5.5v, slow strong drive mode 90/10% vddio into 25 pf - - 7 mhz 1.71v < vddio < 3.3v, slow strong drive mode 90/10% vddio into 25 pf - - 3.5 mhz fgpioin gpio input operating frequency 1.71v < vddio < 5.5v 90/10% vddio - - 79 mhz [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 60 of 85 11.4.2 sio table 11-10. sio dc specifications parameter description conditions min typ max units vinref input voltage reference (differential input mode) 0.5 - 0.52 vddio v voutref output voltage reference (regulated output mode) vddio > 3.7 1 - vddio-1 v vddio < 3.7 1 - vddio - 0.5 v vih input voltage high threshold gpio mode cmos input 0.7 vddio - - v differential input mode with hysteresis vinref+0.05 - - v vil input voltage low threshold gpio mode cmos input - - 0.3 vddio v differential input mode with hysteresis - - vinref-0.05 v voh output voltage high unregulated mode ioh = 4 ma, vddio = 3.3v vddio - 0.4 - - v regulated mode ioh = 1 ma voutref-0.6 - voutref+0.2 v regulated mode ioh = 0.1 ma voutref-0.25 - voutref+0.2 v vol output voltage low vddio = 3.30v, iol = 25 ma - - 0.8 v vddio = 1.80v, iol = 4 ma - - 0.4 v rpullup pull up resistor 4 5.6 8 k rpulldown pull down resistor 4 5.6 8 k iil input leakage current (absolute value) [9] vih < vddsio 25c, vddsio = 3.0v, vih = 3.0v - - 14 na vih > vddsio 25c, vddsio = 0v, vih = 3.0v - - 10 a cin input capacitance [9] --7pf vh input voltage hysteresis (schmitt-trigger) [9] single ended mode (gpio mode) -40-mv differential mode - 50 - mv idiode current through protection diode to vssio --100a table 11-11. sio ac specifications parameter description conditions min typ max units trisef rise time in fast strong mode (90/10%) [9] cload = 25 pf, vddio = 3.3v 1 - 12 ns tfallf fall time in fast strong mode (90/10%) [9] cload = 25 pf, vddio = 3.3v 1 - 12 ns trises rise time in slow strong mode (90/10%) [9] cload = 25 pf, vddio = 3.0v 10 - 75 ns tfalls fall time in slow strong mode (90/10%) [9] cload = 25 pf, vddio = 3.0v 10 - 60 ns [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 61 of 85 11.4.3 usbio fsioout sio output operating frequency 3.3v < vddio < 5.5v, unregulated output (gpio) mode, fast strong drive mode 90/10% vddio into 25 pf - - 33 mhz 1.71v < vddio < 3.3v, unregulated output (gpio) mode, fast strong drive mode 90/10% vddio into 25 pf - - 16 mhz 3.3v < vddio < 5.5v, unregulated output (gpio) mode, slow strong drive mode 90/10% vddio into 25 pf - - 5 mhz 1.71v < vddio < 3.3v, unregulated output (gpio) mode, slow strong drive mode 90/10% vddio into 25 pf - - 4 mhz 3.3v < vddio < 5.5v, regulated output mode, fast strong drive mode output continuously switching into 25 pf --20mhz 1.71v < vddio < 3.3v, regulated output mode, fast strong drive mode output continuously switching into 25 pf --10mhz 1.71v < vddio < 5.5v, regulated output mode, slow strong drive mode output continuously switching into 25 pf --2.5mhz fsioin sio input operating frequency 1.71v < vddio < 5.5v 90/10% vddio - - 79 mhz table 11-12. usbio dc specifications parameter description conditions min typ max units rusbi usb d+ pull up resistance with idle bus 0.900 - 1.575 k rusba usb d+ pull up resistance while receiving traffic 1.425 - 3.090 k vohusb static output high 15 k 5% to vss, internal pull up enabled 2.8 - 3.6 v volusb static output low 15 k 5% to vss, internal pull up enabled --0.3v vohgpio output voltage high, gpio mode ioh = 4 ma, vddio 3v 2.4 - - v volgpio output voltage low, gpio mode iol = 4 ma, vddio 3v - - 0.3 v vdi differential input se nsitivity |(d+)-(d-)| - - 0.2 v vcm differential input common mode range 0.8 - 2.5 v vse single ended receiver threshold 0.8 - 2 v rps2 ps/2 pull up resistance in ps/2 mode, with ps/2 pull up enabled 3-7k rext external usb series resistor in series with each usb pin 21.78 (-1%) 22 22.22 (+1%) zo usb driver output impedance including rext 28 - 44 cin usb transceiver input capacitance - - 20 pf iil input leakage current (absolute value) 25c, vddio = 3.0v - - 2 na table 11-11. sio ac specifications (continued) parameter description conditions min typ max units [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 62 of 85 11.4.4 xres table 11-13. usbio ac specifications parameter description conditions min typ max units tdrate full-speed data rate average bit rate 12 - 0.25% 12 12 + 0.25% mhz tjr1 receiver data jitter tolerance to next transition -8 - 8 ns tjr2 receiver data jitter tolerance to pair transition -5 - 5 ns tdj1 driver differential jitter to next transition -3.5 - 3.5 ns tdj2 driver differential jitter to pair transition -4 - 4 ns tfdeop source jitter for differential transition to se0 transition -2 - 5 ns tfeopt source se0 interval of eop 160 - 175 ns tfeopr receiver se0 interval of eop 82 - - ns tfst width of se0 interval during differential transition --14ns fgpio_out gpio mode output operating frequency 3v vddd 5.5v - - 20 mhz vddd = 1.71v - - 6 mhz tr_gpio rise time, gpio mode, 10%/90% vddd vddd > 3v, 25 pf load 1 - 12 ns vddd = 1.71v, 25 pf load 4 - 40 ns tf_gpio fall time, gpio mode, 90%/10% vddd vddd > 3v, 25 pf load 1 - 12 ns vddd = 1.71v, 25 pf load 4 - 40 ns table 11-14. usb driver ac specifications parameter description conditions min typ max units tr transition rise time 4 - 20 ns tf transition fall time 4 - 20 ns tr rise/fall time matching 90% - 111% vcrs output signal crossover voltage 1.3 - 2 v table 11-15. xres dc specifications parameter description conditions min typ max units vih input voltage high threshold cmos input, prt[x]ctl = 0 0.7 vddio - - v vil input voltage low threshold cmos input, prt[x]ctl = 0 - - 0.3 vddio v rpullup pull up resistor 4 5.6 8 k cin input capacitance [9] -3 pf vh input voltage hysteresis (schmitt-trigger) [9] -100-mv idiode current through protection diode to vddio and vssio --100a table 11-16. xres ac specifications parameter description conditions min typ max units treset reset pulse width 1 - - s [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 63 of 85 11.5 analog peripherals specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.5.1 voltage reference 11.5.2 sar adc table 11-17. voltage reference specifications parameter description conditions min typ max units vref precision reference 1.023 (-0.1%) 1.024 1.025 (+0.1%) v table 11-18. sar adc dc specifications parameter description conditions min typ max units resolution - - 12 bits number of channels - single ended - - no of gpio number of channels - differential differential pair is formed using a pair of neighboring gpio. --no of gpio/2 monotonicity [9] yes - - gain error - - 0.1 % input offset voltage - - 0.2 mv current consumption - - 500 a input voltage range - single ended [9] vssa - vdda v input voltage range - differential [9] vssa - vdda v input resistance [9] -- 2 k cin input capacitance [9] 78 9 pf table 11-19. sar adc ac specifications parameter description conditions min typ max units sample & hold droop [9] -- 1v/s psrr power supply rejection ratio [9] 80 - - db cmrr common mode rejection ratio 80 - - db sample rate [9] -- 1msps snr signal-to-noise ratio (snr) [9] 70 - - db input bandwidth [9] -500 - khz inl integral non linearity [9] internal reference - - 1lsb dnl differential non linearity [9] internal reference - - 1lsb thd total harmonic distortion [9] - - 0.005 % [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 64 of 85 11.5.3 analog globals 11.5.4 temperature sensor table 11-20. analog globals ac specifications parameter description conditions min typ max units rppag resistance pin-to-pin through analog global [12] vdda = 3.0v - 939 1461 vdda = 1.65v - 633 1012 rppmuxbus resistance pin-to-pin through analog mux bus [12] vdda = 3.0v - 721 1135 vdda = 1.65v - 515 843 bwag 3 db bandwidth of analog globals vdda = 3.0v 24 39 - mhz vdda = 1.65v 36 56 - mhz cmrrag common mode rejection for differential signals vdda = 3.0v 85 91 - db vdda = 1.65v 87 93 - db note 12. the resistance of the analog global and analog mux bus is high if vdda 2.7v, and the chip is in either sleep or hi bernate mode. use of analog global and analog mux bus under these conditions is not recommended. table 11-21. temperature sensor specifications parameter description conditions min typ max units temp sensor accuracy -40 to +140 range - 5 - c [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 65 of 85 11.5.5 lcd direct drive table 11-22. lcd direct drive dc specifications parameter description conditions min typ max units icc lcd operating current 32x4 segment display at 30 hz. segment capacitance is < 500 pf [14] . -15- a v bias lcd bias range vdda must be 3v or higher 2.048 - 5.325 v lcd bias step size - 25.8 - mv lcd capacitance per segment/common driver drivers may be combined. - 500 5000 pf long term segment offset - - 10 mv iout per segment driver strong drive 120 160 200 a weak drive - 0.5 - a weak drive 2 - 1 - a icc per segment driver strong drive 220 260 300 a weak drive - 11 - a weak drive 2 - 22 - a no drive - <25 - na static (1 common) icc lcd lcd system operating current vbias = 5v number of lcd pins: 33 (32x1) number of segments: 32 [13] -12- a icc lcd lcd system operating current vbias = 3v number of lcd pins: 33 (32x1) number of segments: 32 [13] -10- a 1/4 duty (4 commons) icc lcd lcd system operating current vbias = 5v number of lcd pins: 36 (32x4) number of segments: 128 [13] -24- a icc lcd lcd system operating current vbias = 3v number of lcd pins: 36 (32x4) number of segments: 128 [13] -21- a 1/16 duty (16 commons) icc lcd lcd system operating current vbias = 5v number of lcd pins: 48 (32x16) number of segments: 512 [13] -93- a icc lcd lcd system operating current vbias = 3v number of lcd pins: 48 (32x16) number of segments: 512 [13] -83- a notes 13. additional conditions: all segments on; 2000 pf glass capacita nce; type a waveform; 32 hz lcd refresh rate; operating temper ature = 25c; boost converter not used. 14. connecting an actual lcd display increases the current consumption based on the size of the lcd glass. table 11-23. lcd direct drive ac specifications parameter description conditions min typ max units f lcd lcd frame rate 10 50 150 hz [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 66 of 85 11.6 digital peripherals specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.6.1 timer 11.6.2 counter table 11-24. timer dc specifications parameter description conditions min typ max units block current consumption 16-bit timer, at listed input clock frequency ---a 3 mhz -8-a 12 mhz - 30 - a 40 mhz - 120 - a table 11-25. timer ac specifications parameter description conditions min typ max units operating frequency dc - 40 mhz capture pulse width (internal) 25 - - ns capture pulse width (external) 30 - - ns timer resolution 25 - - ns enable pulse width 25 - - ns enable pulse width (external) 30 - - ns reset pulse width 25 - - ns reset pulse width (external) 30 - - ns table 11-26. counter dc specifications parameter description conditions min typ max units block current consumption 16-bit c ounter, at listed input clock frequency ---a 3 mhz -8-a 12 mhz - 30 - a 40 mhz - 120 - a table 11-27. counter ac specifications parameter description conditions min typ max units operating frequency dc - 40 mhz capture pulse 25 - - ns resolution 25 - - ns pulse width 25 - - ns pulse width (external) 30 ns enable pulse width 25 - - ns enable pulse width (external) 30 - - ns reset pulse width 25 - - ns reset pulse width (external) 30 - - ns [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 67 of 85 11.6.3 pulse width modulation 11.6.4 i 2 c 11.6.5 controller area network [15] table 11-28. pwm dc specifications parameter description conditions min typ max units block current consumption 16-bit pwm, at listed input clock frequency ---a 3 mhz -8-a 12 mhz - 30 - a 40 mhz - 120 - a table 11-29. pwm ac specifications parameter description conditions min typ max units operating frequency dc - 40 mhz pulse width 25 - - ns pulse width (external) 30 - - ns kill pulse width 25 - - ns kill pulse width (external) 30 - - ns enable pulse width 25 - - ns enable pulse width (external) 30 - - ns reset pulse width 25 - - ns reset pulse width (external) 30 - - ns table 11-30. fixed i 2 c dc specifications parameter description conditions min typ max units block current consumption enabled, configured for 100 kbps - - 64 a enabled, configured for 400 kbps - - 74 a wake from sleep mode - - tbd a table 11-31. fixed i 2 c ac specifications parameter description conditions min typ max units bit rate - - 1 mbps note 15. refer to iso 11898 specification for details. table 11-32. can dc specifications parameter description conditions min typ max units block current consumption 500 kbps - - 285 a 1 mbps - - 330 a table 11-33. can ac specifications parameter description conditions min typ max units bit rate minimum 8 mhz clock - - 1 mbit [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 68 of 85 11.6.6 usb 11.7 memory specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.7.1 flash 11.7.2 eeprom table 11-34. usb dc specifications parameter description conditions min typ max units operating current usb enabled bus idle - 0.68 - ma table 11-35. flash dc specifications parameter description conditions min typ max units erase and program voltage vddd pin 1.71 - 5.5 v table 11-36. flash ac specifications parameter description conditions min typ max units twrite block write time (erase + program) - - 15 ms terase block erase time - - 10 ms block program time - - 5 ms tbulk bulk erase time (256 kb) [16] --80ms sector erase time (16 kb) [16] --15ms total device program time (including jtag, etc.) - - 5 seconds flash endurance 100k - - program/ erase cycles flash data retention time rete ntion period measured from last erase cycle 20 - - years note 16. ecc not included table 11-37. eeprom dc specifications parameter description conditions min typ max units erase and program voltage 1.71 - 5.5 v table 11-38. eeprom ac specifications parameter description conditions min typ max units twrite single byte erase/write cycle time - 2 15 ms eeprom endurance 1m - - program/ erase cycles eeprom data retention time rete ntion period measured from last erase cycle (up to 100k cycles) 20 - - years [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 69 of 85 11.7.3 nonvolatile latches (nvl)) 11.7.4 sram table 11-39. nvl dc specifications parameter description conditions min typ max units erase and program voltage vddd pin 1.71 - 5.5 v table 11-40. nvl ac specifications parameter description conditions min typ max units nvl endurance programmed at 25c 1k - - program/ erase cycles programmed at 0 to 70c 100 - - program/ erase cycles nvl data retention time programmed at 25c 20 - - years programmed at 0 to 70c 20 - - years table 11-41. sram dc specifications parameter description conditions min typ max units vsram sram retention voltage 1.2 - - v table 11-42. sram ac specifications parameter description conditions min typ max units fsram sram operating frequency dc - 40 mhz [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 70 of 85 11.7.5 external memory interface figure 11-1. asynchronous read cycle timing table 11-43. asynchronous read cycle specifications parameter description conditions min typ max units t emif clock period 30.3 - - ns tcel em_cen low time 2*t-1 - 2*t+2 ns taddrv em_cen low to em_addr valid - - 5 ns taddrh address hold time after em_oen high 2 - - ns toev em_cen low to em_oen low -5 - 5 ns toel em_oen low time 2*t-1 - 2*t+2 ns toeh em_oen high to em_cen high hold time -5 - 5 ns tdoesu data to em_oen high setup time t+20 - - ns tdcesu data to em_cen high setup time t+20 - - ns tdoeh data hold time after em_oen high 3 - - ns tdceh data hold time after em_cen high 3 - - ns em_addr em_cen em_oen em_data em_wen address data tcel taddrv taddrh toev toel toeh tdcesu tdoesu tdceh tdoeh [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 71 of 85 figure 11-2. asynchronous write cycle timing table 11-44. asynchronous write cycle specifications parameter description conditions min typ max units t emif clock period 30.3 - - ns taddrv em_cen low to em_addr valid - - 5 ns taddrh address hold time after em_wen high t+2 - - ns tcel em_cen low time 2*t-1 - 2*t+2 ns twev em_cen low to em_wen low -5 - 5 ns twel em_wen low time t-1 - t+2 ns tweh em_wen high to em_cen high hold time t - - ns tdcev em_cen low to data valid - - 7 ns tdweh data hold time after em_wen high t - - ns address data taddrv taddrh tcel twev twel tweh tdcev tdweh em_ data em_ oen em_ cen em_ addr [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 72 of 85 figure 11-3. synchronous read cycle timing table 11-45. synchronous read cycle specifications parameter description conditions min typ max units t emif clock period 30.3 - - ns tcp em_clock period 30.3 - - ns tceld em_clock low to em_cen low - 5 ns tcehd em_clock high to em_cen high t/2 - 2 - - ns taddrv em_clock low to em_addr valid - - 5 ns taddriv em_clock high to em_addr invalid t/2 - 2 - - ns toeld em_clock low to em_oen low - - 5 ns toehd em_clock high to em_oen high t+2 - - ns tds data valid before em_clock high 20 - - ns tdh data valid after em_clock high 2 - - ns tadscld em_clock low to em_adscn low - - 5 ns tadschd em_clock high to em_adscn high t/2 - 2 - - ns address tcp tceld taddrv tcehd taddriv toehd toeld tds tadscld tadschd data tdh em_ clock em_ cen em_ addr em_ oen em_ data em_ adscn [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 73 of 85 figure 11-4. synchronous write cycle timing table 11-46. synchronous write cycle specifications parameter description conditions min typ max units t emif clock period 30.3 - - ns tcp em_clock period 30.3 - ns tceld em_clock low to em_cen low - 5 ns tcehd em_clock high to em_cen high t/2 - 2 - ns taddrv em_clock low to em_addr valid - 5 ns taddriv em_clock high to em_addr invalid t/2 - 2 - ns tweld em_clock low to em_wen low - 5 ns twehd em_clock high to em_wen high t/2 - 2 - ns tds data valid after em_clock low - 5 ns tadscld em_clock low to em_adscn low - 5 ns tadschd em_clock high to em_adscn high t/2 - 2 - ns address tcp tceld taddrv tcehd taddriv twehd tweld tds data tadscld tadschd em_ clock em_ cen em_ addr em_ wen em_ data em_ adscn [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 74 of 85 11.8 psoc system resources specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.8.1 por with brown out 11.8.2 voltage monitors table 11-47. power on reset (p or) with brown ou t dc specifications parameter description conditions min typ max units imprecise por (ipor) rising trip voltage 0.8 - 1.45 v falling trip voltage 0.75 - 1.4 v hysteresis 15 - 200 mv precise por (ppor) rising trip voltage 1.588 1.620 1.652 v falling trip voltage 1.562 1.594 1.626 v table 11-48. power on reset (p or) with brown ou t ac specifications parameter description conditions min typ max units ppor_tr response time - - 1.00e+00 s table 11-49. voltage monitors dc specifications parameter description conditions min typ max units lvi trip voltage lvi_a/d_sel[3:0] = 0000b 1.667 1.701 1.735 v lvi_a/d_sel[3:0] = 0001b 1.914 1.953 1.992 v lvi_a/d_sel[3:0] = 0010b 2.158 2.202 2.246 v lvi_a/d_sel[3:0] = 0011b 2.404 2.453 2.502 v lvi_a/d_sel[3:0] = 0100b 2.651 2.705 2.759 v lvi_a/d_sel[3:0] = 0101b 2.895 2.954 3.013 v lvi_a/d_sel[3:0] = 0110b 3.144 3.208 3.272 v lvi_a/d_sel[3:0] = 0111b 3.387 3.456 3.525 v lvi_a/d_sel[3:0] = 1000b 3.629 3.703 3.777 v lvi_a/d_sel[3:0] = 1001b 3.875 3.954 4.033 v lvi_a/d_sel[3:0] = 1010b 4.117 4.201 4.285 v lvi_a/d_sel[3:0] = 1011b 4.362 4.451 4.540 v lvi_a/d_sel[3:0] = 1100b 4.607 4.701 4.795 v lvi_a/d_sel[3:0] = 1101b 4.879 4.979 5.079 v lvi_a/d_sel[3:0] = 1110b 5.107 5.211 5.315 v lvi_a/d_sel[3:0] = 1111b 5.356 5.465 5.574 v hvi trip voltage 5.630 5.745 5.860 v [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 75 of 85 11.8.3 interrupt controller 11.8.4 jtag interface 11.8.5 swd interface 11.8.6 tpiu interface table 11-50. voltage monitors ac specifications parameter description conditions min typ max units response time - - 1.00e+00 s table 11-51. interrupt controller ac specifications parameter description conditions min typ max units delay from interrupt signal input to isr code execution from main line code includes worse case completion of longest instruction ???? with ?? cycles - - 20 tcy cpu delay from interrupt signal input to isr code execution from isr code includes worse case completion of longest instruction ???? with ?? cycles - - 20 tcy cpu table 11-52. jtag interface ac specifications [9] parameter description conditions min typ max units tck frequency - - 8 mhz tck low 6.5 - - ns tck high 5.5 - - ns tdi, tms setup before tck high 2 - - ns tdi, tms hold after tck high 3 - - ns tdo hold after tck high 4 - - ns tck low to tdo valid 4 16 - ns tck to device outputs valid - - 18 ns table 11-53. swd interface ac specifications [9] parameter description conditions min typ max units swdclk frequency - - 8 mhz table 11-54. tpiu interface ac specifications [9] parameter description conditions min typ max units traceport (traceclk) frequency - - 33 mhz swv bit rate - - 33 mbit [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 76 of 85 11.9 clocking specifications are valid for -40c ta 85c and tj 100c, except where noted . specifications are valid for 1.71v to 5.5v, except where noted. 11.9.1 32 khz external crystal 11.9.2 internal main oscillator) table 11-55. 32 khz external crystal dc specifications [9] parameter description conditions min typ max units icc operating current low power mode - 0.25 - a cl external crystal capacitance - 6 - pf dl drive level - - 1 w table 11-56. 32 khz external crystal ac specifications parameter description conditions min typ max units f frequency - 32.768 - khz dc output duty cycle [9] 20 50 80 % ton startup time high power mode - 1 - s table 11-57. imo dc specifications parameter description conditions min typ max units supply current 48 mhz - 30 - a 24 mhz - non usb mode - 160 - a 24 mhz - usb mode with oscillator locking to usb bus - 500 - a 12 mhz - 100 - a 6 mhz -80 - a 3 mhz -70 - a table 11-58. imo ac specifications parameter description conditions min typ max units fimo imo frequency stability (with factory trim) 40 mhz -5 - 5 % 24 mhz - non usb mode -4 - 4 % 24 mhz - usb mode with oscillator locking to usb bus -0.25 - 0.25 % 12 mhz -3 - 3 % 6 mhz -2 - 2 % 3 mhz -1 - 1 % startup time [9] from enable (during normal system operation) or wakeup from low power state --10s [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 77 of 85 11.9.3 internal low speed oscillator 11.9.4 external crystal oscillator jp-p jitter (peak to peak) [9] f = 24 mhz - 0.9 - ns f = 3 mhz - 1.6 - ns jperiod jitter (long term) [9] f = 24 mhz - 0.9 - ns f = 3 mhz - 12 - ns table 11-58. imo ac specifications (continued) parameter description conditions min typ max units table 11-59. ilo dc specifications parameter description conditions min typ max units icc operating current, includes sleep timer and wdt fout = 1 khz - 0.3 - a fout = 32 khz - 0.5 - a fout = 100 khz - 0.6 - a table 11-60. ilo ac specifications [9] parameter description conditions min typ max units startup time turbo mode - 0.1 3 ms startup time non-turbo mode, pd_mode = 0 - 0.6 2 ms startup time non-turbo mode, pd_mode = 1 - 0.8 17 ms duty cycle 45 50 55 % filo ilo frequencies (trimmed) 100 khz 80 100 130 khz 32 khz 26 32 43 khz 1 khz 0.75 1 1.65 khz ilo frequencies (untrimmed) 100 khz 55 100 160 khz 32 khz 18 32 56 khz 1 khz 0.55 1 1.75 khz table 11-61. eco ac specifications parameter description conditions min typ max units f crystal frequency range 4 - 33 mhz dc duty cycle [9] 40 50 60 % jp-p jitter (peak to peak) [9] sio, gpio - 200 - ps jperiod jitter (long term) [9] sio, gpio - 200 - ps [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 78 of 85 11.9.5 external clock reference 11.9.6 phase-locked loop table 11-62. external clock reference ac specifications [9] parameter description conditions min typ max units external frequency range 0 - 33 mhz input duty cycle range measured at vddio/2 30 50 70 % input edge rate vil to vih 0.1 - - v/ns table 11-63. pll dc specifications parameter description conditions min typ max units idd pll operating current fref = 3 mhz, fvco=24 mhz - 560 - a table 11-64. pll ac specifications parameter description conditions min typ max units fpllinpre pll prescaler input frequency 1 - 48 mhz fpllin pll input frequency 1 - 3 mhz fpllout pll output frequency 24 - 80 mhz lock time at startup - - 250 s jperiod-rms jitter (rms) [9] --250ps pll output duty cycle all pl l output frequencies 45 - 55 % [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 79 of 85 12. ordering information in addition to the features listed in ta b l e 1 2 - 1 , every cy8c52 device includes: up to 256k flash, 64k sram, 2k eeprom, a precision on-chip voltage reference, precision oscillat ors, flash, ecc, dma, a fixed function i 2 c, jtag/swd programming and debug, external memory interface, and more. in addition to these features, the fl exible udbs and analog subsection support a wide range of peri ph- erals. to assist you in selecting the ideal part, psoc creato r makes a part recommendation after you choose the components requ ired by your application. all cy8c52 derivative s incorporate device and flash security in user-selectable security levels; see trm f or details . table 12-1. cy8c52 family with arm cortex-m3 cpu part number mcu core analog digital i/o [18] package jtag id [19] cpu speed (mhz) flash (kb) sram (kb) eeprom (kb) lcd segment drive adc dac comparators sc/ct analog blocks opamps dfb udbs [17] 16-bit timer/pwm fs usb can 2.0b total i/o gpio sio usbio 32 kb flash cy8c5245pvi-112 40 32 8 2 ? 1x12-bit sar 0 2 0 0 - 20 4 - - 29 25 4 0 48-ssop 0x0e170069 cy8c5245pvi-113 40 32 8 2 ? 1x12-bit sar 0 2 0 0 - 20 4 ? - 31 25 4 2 48-ssop 0x0e171069 64 kb flash cy8c5246axi-038 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 70 62 8 0 100-tqfp 0x0e126069 cy8c5246lti-087 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 46 38 8 0 68-qfn 0x0e157069 cy8c5246pvi-071 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 29 25 4 0 48-ssop 0x0e147069 cy8c5246axi-054 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 72 62 8 2 100-tqfp 0x0e136069 cy8c5246lti-029 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 48 38 8 2 68-qfn 0x0e11d069 cy8c5246pvi-092 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 31 25 4 2 48-ssop 0x0e15c069 cy8c5246axi-093 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 70 62 8 0 100-tqfp 0x0e15d069 cy8c5246pvi-012 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 29 25 4 0 48-ssop 0x0e10c069 cy8c5246axi-002 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 72 62 8 2 100-tqfp 0x0e102069 cy8c5246pvi-091 40 64 16 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 31 25 4 2 48-ssop 0x0e15b069 128 kb flash cy8c5247axi-086 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 70 62 8 0 100-tqfp 0x0e156069 cy8c5247lti-033 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 46 38 8 0 68-qfn 0x0e121069 cy8c5247pvi-066 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 29 25 4 0 48-ssop 0x0e142069 cy8c5247axi-051 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 72 62 8 2 100-tqfp 0x0e133069 cy8c5247lti-089 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 48 38 8 2 68-qfn 0x0e159069 cy8c5247pvi-068 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 31 25 4 2 48-ssop 0x0e144069 cy8c5247axi-013 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 70 62 8 0 100-tqfp 0x0e10d069 cy8c5247pvi-082 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 29 25 4 0 48-ssop 0x0e152069 cy8c5247axi-110 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 72 62 8 2 100-tqfp 0x0e16e069 cy8c5247pvi-074 40 128 32 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 31 25 4 2 48-ssop 0x0e14a069 notes 17. udbs support a wide variety of functionality including spi, lin, uart, timer, counter, pwm, prs, and others. individual func tions may use a fraction of a udb or multiple udbs. multiple functions can share a single udb. see example peripherals on page 33 for more information on how udbs may be used. 18. the i/o count includes all types of digital i/o: gpio, sio, and the two usb i/o. see i/o system and routing on page 26 for details on the functionality of each of these types of i/o. 19. the jtag id has three major fields. the most significant nibble (left digit) is the version, followed by a 2 byte part numbe r and a 3 nibble manufacturer id. [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 80 of 85 part number mcu core analog digital i/o [18] package jtag id [19] cpu speed (mhz) flash (kb) sram (kb) eeprom (kb) lcd segment drive adc dac comparators sc/ct analog blocks opamps dfb udbs [17] 16-bit timer/pwm fs usb can 2.0b total i/o gpio sio usbio 256 kb flash cy8c5248axi-050 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 70 62 8 0 100-tqfp 0x0e132069 cy8c5248lti-041 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 46 38 8 0 68-qfn 0x0e129069 CY8C5248PVI-101 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - - 29 25 4 0 48-ssop 0x0e165069 cy8c5248axi-047 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 72 62 8 2 100-tqfp 0x0e12f069 cy8c5248lti-030 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 48 38 8 2 68-qfn 0x0e11e069 cy8c5248pvi-024 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ? - 31 25 4 2 48-ssop 0x0e118069 cy8c5248axi-078 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 70 62 8 0 100-tqfp 0x0e14e069 cy8c5248pvi-028 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 - ? 29 25 4 0 48-ssop 0x0e11c069 cy8c5248axi-059 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 72 62 8 2 100-tqfp 0x0e13b069 cy8c5248pvi-009 40 256 64 2 ? 1x12-bit sar 0 2 0 0 - 24 4 ?? 31 25 4 2 48-ssop 0x0e109069 table 12-1. cy8c52 family with arm cortex-m3 cpu [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 81 of 85 12.1 part numbering conventions psoc 5 devices follow the part numbering convention described below. all fields are single character alphanumeric (0, 1, 2, ?, 9, a, b, ?, z) unless stated otherwise. cy8cabcdefg-xxx ? a: architecture ? 3: psoc 3 ? 5: psoc 5 ? b: family group within architecture ? 2: cy8c52 family ? 3: cy8c53 family ? 4: cy8c54 family ? 5: cy8c55 family ? c: speed grade ? 4: 40 mhz ? 8: 80 mhz ? d: flash capacity ? 5: 32 kb ? 6: 64 kb ? 7: 128 kb ? 8: 256 kb ? ef: package code ? two character alphanumeric ? ax: tqfp ? lt: qfn ? pv: ssop ? g: temperature range ? c: commercial ? i: industrial ? a: automotive ? xxx: peripheral set ? three character numeric ? no meaning is associated with these three characters all devices in the psoc 5 cy8c52 family comp ly to rohs-6 specifications, demonstrati ng the commitment by cypress to lead-free products. lead (pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. cy press uses nickel-palladium-gold (nipdau) technology for the majority of leadframe-based packages. a high level review of the cypress pb-free position is available on our website. specific package information is also available . package material declaration datasheets (pmdds) identify all substanc es contained within cypress packages. pmdds also confirm the absence of many banned substances. the info rmation in the pmdds will help cypress cust omers plan for recycling or other "end of life" requirements. architecture cypress prefix family group within architecture speed grade flash capacity package code temperature range peripheral set 5: psoc5 4: 40 mhz 8: 256 kb pv: ssop i: industrial examples cy8c 5 2 v p 8 4ix x -x 2: cy8c52 family [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 82 of 85 13. packaging figure 13-1. 48-pin (300 mil) ssop package outline table 13-1. package characteristics parameter description conditions min typ max units ta operating ambient temperature -40 25 85 c tj operating junction temperature -40 - 100 c tja package ja (48 ssop) - 36.87 - c/watt tja package ja (68 qfn) - 10.93 - c/watt tja package ja (100 tqfp) - 29.50 - c/watt tjc package jc (48 ssop) - 25.48 - c/watt tjc package jc (68 qfn) - 6.08 - c/watt tjc package jc (100 tqfp) - 7.32 - c/watt pb-free assemblies (20s to 40s) - sn-ag-cu solder paste reflow temperature 235 - 245 c pb-free assemblies (20s to 40s) - sn-pb solder paste reflow temper- ature 205 - 220 c 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 83 of 85 figure 13-2. 68-pin qfn 8x8 with 0.4 mm pitch package outline (sawn version) figure 13-3. 100-pin tqfp (14 x 14 x 1.4 mm) package outline top view 0.200 ref pin 1 dot laser mark 1 8 3 4 3 5 5 1 5 2 6 8 1 1 7 0.08 c seating plane 0.05 max bottom view 1 0.4000.100 0.400 pitch 6 8 5 2 5 1 3 5 3 4 1 8 1 7 8.0000.100 8.0000.100 0.9000.100 6.40 ref 6.40 ref side view 0.200.05 5.70.10 pad exposed solderable 5.70.10 pin1 id r 0.20 001-09618 *c 0.220.05 0.50 14.000.05 sq 16.000.25 sq 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. gauge plane 0.20 max. 0.15 max. 0.20 max. 1 100 r 0.08 min. 0.20 max. 76 75 51 25 26 50 0 0 12.0000 0.08 see detail a detail a seating plane note: pkg. can have or top left corner chamfer 4 corners chamfer note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 51-85048-*c [+] feedback
preliminary psoc ? 5: cy8c52 family data sheet document number: 001-55034 rev. *a page 84 of 85 14. revision history description title: psoc ? 5: cy8c52 family data sheet programmable system-on-chip (psoc ? ) document number: 001-55034 rev. ecn no. submission date orig. of change description of change ** 2759055 09/02/09 mkea new data sheet for new device cy8c52 family data sheet. *a 2824626 12/09/09 mkea updated i2c section to reflec t 1 mbps. updated table 11-6 and 11- 7 (boost ac and dc specs); also added shottky diode specs. changed current for sleep/hibernate mode to include sio; added footnote to analog global specs. updated figures 1-1, 6-2, 7-14, and 8-1. updated table 6-2 and table 6-3 (hibernate and sleep rows) and power modes section. updated gpio and sio ac specifications. updated gain error in idac and vdac specifications. updated description of vdda spec in table 11-1 and removed gpio clamp current parameter. moved filo from ilo dc to ac table. added pcb layout and pcb schematic diagrams. updated fgpioout spec (table 11-9). added duty cycle frequency in pll ac spec table. added note for sleep and hibernate modes and active mode specs in table 11-2. linked url in section 10.3 to psoc creator site. updated ja and jc values in table 13-1. updated single sample mode and fast fir mode sections. updated input resistance specification in del-sig adc table. added tio_init parameter. updated pga and ugb ac specs. removed spc adc. updated boost converter section. added section 'sio as comparator'; u pdated hysteresis spec (differential mode) in table 11-10. updated vbat condition and deleted vstart parameter in table 11-6. removed reference to idle mode. cdt 59671: updated footnotes and adc column in ordering information. removed csa (section 8.7). updated imo table and number of udbs [+] feedback
document number: 001-55034 rev. *a revised december 03, 2009 page 85 of 85 capsense ? , psoc ? 3, psoc ? 5, and psoc ? creator? are trademarks and psoc ? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublic ensed associated companies conve ys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. arm is a registered trademark, and keil, and realview are trademarks, of arm limited. all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary psoc ? 5: cy8c52 family data sheet ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the so le purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or im plied, with regard to this mate rial, including, but not limited to, the implied warranties of merchantability and fitness for a particul ar purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 15. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com [+] feedback

▲Up To Search▲

Price & Availability of CY8C5248PVI-101

	To Download CY8C5248PVI-101 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .